SU1478229A1 - Analog four-quadrant multiplier - Google Patents

Abstract

The invention relates to electrical computing devices and can be used in analog computers. The aim of the invention is to expand the dynamic range, increase accuracy and reduce power consumption. An analog four-quadrant multiplier contains three voltage-to-current converters, two current-voltage converters, two load resistors, twenty-four amplifying field-effect transistors, six adjustable bias voltage sources, twelve adjustable bias voltage sources, input busbars of the first factor-factor, the input buses of the second signal multiplier, the output buses, the power buses, the reference voltage bus. The operation of the multiplier is based on the implementation of the variable steepness method. 4 hp f-ly, 6 ill.

Description

one

The invention relates to electrical computing devices and can be used in analog computers.

The aim of the invention is to expand the dynamic range, increase accuracy and reduce power consumption.

Figure 1 shows the functional diagram of the analog four-quadrant multiplier; Figures 2 and 3 are functional diagrams of adjustable voltage sources of mixing; Figures 4 and 5 are functional diagrams of controlled voltage sources; figure 6 is a graph of the output currents of the third Converter

voltage to current from input voltage (continuous line) and the transfer characteristic curve of the third voltage to current converter, explaining its principle of operation (dotted line).

The multiplier contains the first to the third voltage-to-current converters 1-3, the first 4 and second 5 current-to-voltage converters, the first b and the second 7 load resistors, the first through twenty-fourth amplifying field effect transistors 8-31, the first to the sixth adjustable sources 32-37 bias voltage of the first to the twelfth adjustable sources 38-49 mate voltage,

oo

1hE K

the first 50 and second 51 input buses of the first signal multiplier, the first 52 and second 53 input buses of the second signal multiplier, the first 54 and second 55 output spikes, the first 56 and second 57 power supply buses, the reference voltage bus 58, twenty-fifth and twenty-sixth 60 amplifying field effect transistors, first adjustable bias current source 61, first 62 and second 63 outputs and control input 64 of the first to fourth adjustable bias voltage sources, twenty-seventh 65 and twenty-eighth 66 amplifying field effect transistors, second adjustable The primary bias current source 67, the first 68 and second 69 pins, and the input 70 of the control of the fifth and sixth regulated voltage sources biased, from twenty-ninth to thirty-second amplifying field effect transistors 71-74, the first regulated source 75 of the current , the first 76 and second 77 outputs and the control input 78 of the first, second, fifth, sixth, eleventh and twelfth controlled voltage sources of mating, from the thirty-third to the thirty-sixth amplifying field-effect transistors 79-82, the second adjustable source 83 current the first 84 and the second 85 terminals and the control input 86 of the third, fourth and seventh to tenth controlled voltage sources.

The multiplier works as follows.

The principle of operation is based on the implementation of the variable slope method. The inputs of the third voltage converter 3 are supplied with a voltage of the second signal multiplier, which through the third voltage converter 3 and the first 4 and second 5 current-voltage converters control the slope of the first 1 and second 2 voltage-to-current converters which convert the voltage of the first signal to the multiplier to their respective inputs, proportional to the value of the voltage of the second signal to the multiplier. Highly accurate voltage transducers are needed to implement the multiplication method used and ensure high accuracy.

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into current with the ability to adjust the value of their steepness. The first 1, second 2 and third 3 voltage-to-current converters implement a new method of linear conversion of voltage to current, based on the development of the well-known principle of subtracting currents, whose function of voltage is

 k (Ub + U). I2 k (U6 - Ux) e where 1,, I, (1)

currents at the outputs of the voltage to current converter;

UK is the voltage of the first multiplier signal; k, UB - constant parameters. The difference in the currents of expression (1) is linearly dependent on the voltage of the first signal multiplier. This operation is performed using field-effect (including MIS) transistors, the drain current of which in the saturation mode has a quadratic dependence on the voltage between the gate and the source.

An alternative implementation of the well-known principle of subtracting currents is the use of a complementary pair of field (including MIS) transistors with combined sources, the voltage between the gates of which can be controlled by the current flowing through them. This connection of field-effect transistors is used in the proposed multiplier. The use of a reference connection of complementary field-effect transistors allows one to solve the problem of the constant potential difference between the outputs of the controlled voltage sources, since in this case the current flowing through them is constant and is not consumed by other elements.

A common disadvantage of known voltage-to-current converters, implementing the principle of current subtraction, is limiting the permissible input voltage at which one of the pairs of input field-effect transistors goes into cut-off mode, which leads to the output of the voltage-to-current converter from linear operation. However, the difference current linearly depends on the voltage for any value, if the field-effect transistor passes the current in the opposite direction. In the diagram (Fig. 1), the first 1, second 2 and three

Three voltage-to-current converters each contain four pairs of identical field-effect transistors and three pairs of ungrounded regulated voltage sources. In this case, the current from the regulated voltage sources is not rejected, i.e. fixed

For example, the operation of the third converter 3 voltage to current when the voltage of the second signal-multiplier from the first 52 and second 53 input buses is applied to its inputs is divided into three areas.

The value of the voltage between the first and second pins of the fifth 36 and sixth 37 adjustable bias voltage sources, forming the given slope of the third voltage-to-voltage converter 3, should be equal to

 Ub2 + IW-ipo „p, (2)

- where U & H, UOT are permanent parameters; Unwn, Unopp threshold voltages of n-type and p-type conductance field-effect transistors.

The voltage value between the first and second terminals of the ninth 46 and the tenth 47 adjustable voltage sources must be 2 UB, and the voltage between the first and second terminals of the eleventh 48 and twelfth 49 adjustable voltage sources must be equal to 2UBZ, since these sources form a given linearity of the conversion at high input voltages.

In the first area of work, traditionally used in these devices, the input voltage satisfies the inequality

lUyUl ,, +, (3)

where Uy is the voltage of the second signal multiplier.

In this case, the nineteenth 26, twentieth 27, twenty-third 30 and twenty-fourth 31 amplifying field-effect transistors are locked at the gate and do not affect the value of the output current, which is determined by the difference of the drain currents of the fifth 12, sixth 13, twenty-first and 28 twenty-second 29 amplifying field effect transistors and is described by the expression

I, - I9 4k395 (UB (+ UM) Uy, (4)

782296

where k ,, - coefficient taking into account

field effect transistors.

In the second region, the input voltage satisfies the inequality Uy7 Uei + Ua2. (5)

In this case, the sixth 13 and twenty-second 29 amplified field-effect transistors are operated at the gate, and the output current is determined by the difference between the drain currents of the fifth 12, twenty-first 28 and opened nineteenth and 26th and twenty-third 30 amplifying field-effect transistors and is described by the expression (4 ).

In the third region, the input voltage satisfies the inequality. Well: - (im + i62) (6)

20In this mode, the fifth is locked 12

and the twenty-first 28 field-effect transistors, open the twentieth 27 and twenty-fourth 31 field-effect transistors. Therefore, the output current is determined by the difference in currents tTOKOB of the sixth 13, twenty-second 29 and twentieth 27 and twenty-fourth 31 amplifying field-effect transistors and is described by the 30th expression (4).

When a third voltage converter 3 is applied to the input, the input voltage of the second signal multiplier at its first and second outputs 35 currents flow, the values of which satisfy expression (4). The first output current of the third voltage converter 3 is of the first converter 4, the current 40, the quality of which can be used diode-switched transistor (field or MIS), changes the slope of the first converter 1 voltage to current due to

45 changes in voltage values between the first and second terminals of the first 32 and second 33 adjustable sources of bias voltage and the first 38, second 39, third 40 and fourth 5Q 41 controlled sources of voltage. At the same time, the second output current of the third voltage-to-current converter 3 through the second converter l 5 current-voltage changes the slope of the second voltage-current converter 2 due to the change in the voltage values between the first and second terminals of the third 34 and fourth 35 controlled sources displacement; and an additional 42, sixth 43, seventh 44, eighth, 45 adjustable voltage sources. The corresponding values of the output currents of the first 1 and second 2 voltage-to-current converters when the voltage of the first signal factor is supplied to their inputs are described by the expression.

VI

m hzc (U6 + Uy + Ux G,

 (UB + Uv- U) a,

1.4 k (U6- Uy- Ux) ",

gff (and-iu + them)

(7)

Due to the indicated connection (Fig. 1) of the first I and second 2 voltage-to-current converters, the output current of the multiplier is described by the expression

1вых (, + Iu) (1ц + Т-гг), (8) substituted in which the expression (4); get the value of the output current

1st Ux Uy, as well as output voltages.

Substituting expression (6) into expression (5), we get

1OUT

 Y (9)

Output voltage on the first 54 and second 55 output tires

IW UKUy (10)

where R is the resistance of identical first 6 and second 7 load resistors. Methods for implementing controlled bias voltage sources may vary. In the diagram (Fig. 2), the potential difference between the first 62 and second 63 terminals is equal to

l | l / kn + YTZjTp + Unopn + Unop.p, (11) where 1 I is the first regulated current

source 61 bias current, kp - slope, respectively

twenty-fifth; 59 and twenty-sixth 60 amplification field transistors. For adjustable voltage sources, the choice of the ratio of the channel width to the channel length of the twenty-ninth amplifying field-effect transistor 71 is nine times less than the ratio of the channel width to the channel length of the thirtieth amplifying field-effect transistor 72, whose dimensions coincide with the channel sizes of the first 8 and second 9 amplifying field-effect transistors. With this choice, the voltage between the first 76 and the second

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pin 77 is determined by the difference of gate-source voltages of twenty-ninth 71 and thirtieth 72 amplifying field-effect transistors and is equal to

2iT / T, (| 2)

where I is the current of the controlled conjugate current source 75.

When implementing a multiplier in the integral performance, the change in is. for all controlled current sources in proportion to temperature changes in the environment. In accordance with this, the voltages of the controlled bias voltage sources also change in proportion, which leads to the preservation of the accuracy of operation over a wide range of temperatures.

Thus, in the proposed multiplier, there is no relationship between the accuracy of operation, the value of the current consumption and the value of the maximum allowable input voltage. This leads to the fact that the maximum permissible input voltage of the multiplier is limited only by the permissible parameters of the manufacturing process of field-effect transistors: the voltage of the drain-source voltage, the voltage of the gate dielectric in the case of using MIS transistors, as well as the voltage of the sources used nutrition In addition, a constant level of accuracy of operation is maintained throughout the used input voltage range, and the magnitude of the current consumption affects only the value of the bandwidth processed without distortion, and does not affect the value of accuracy at different levels input voltage, i.e. the multiplier has a reduced power consumption. In the multiplier, the voltage is maintained between the first and second pins of the controlled bias voltage sources, since the current from these sources is not drawn by other elements.

Thus, the multiplier has an extended dynamic range, increased accuracy of operation and reduced power consumption.

Claims (1)

Formula invented and 1, Analog four-quadrant multiplier, containing the first and the second current transducers are, for example, in order to expand the dynamic range, increase accuracy and reduce power consumption, the seventh and eighth amplifiers of field conductance, the ninth and twelfth amplifiers, are introduced into the first voltage converter p-j conductivity type of conductors and the first to fourth regulated voltage sources, the thirteenth and fourteenth amplifying field e 15 transistors of n-type conduct to the second voltage converter STI, the fifteenth to seventeenth -to amplifying FETs and p-tipaprovodimosti fifth to eighth voltage sources adjustable coupling, for the third the first and second load resistors, the first voltage to current converter, made on the first and second field-effect transistors of n-type conductivity, and the first and second adjustable sources of bias voltage, the second voltage to current converter, made on the third and fourth field voltage n-type transistors and the third and fourth adjustable bias voltage sources, the third converter, voltage to current made on the fifth and sixth p-type field effect transistors and the fifth and sixth Rui source bias voltage, the gates of the first and the fourth amplifying field-effect transducer; the voltage transducers were introduced into the nineteenth and twentieth p-type conductive field-effect transistors; the twenty-first to twentieth-fourth field amplifiers 25 n-type transistors and ninth-twelfth adjustable mains voltage source, the drain of the eighth amplifying field-effect transistor is connected to the drain of the first amplifying field-effect transistor, the gate of which is connected to the first output of the first adjustable voltage source, the second output of which is connected with shutter seventh The CS of an amplifying field-effect transistor, the source of which is connected to the sources of the first, ninth and eleventh amplifying field-effect transistors, the gate of which is connected to the first terminal of the third adjustable voltage source of conjugation, the second terminal of which is connected to the second output of the first adjustable source of the bias voltage and the gate The ninth intensified zero transis connected to the first terminals of the second and third variable voltage sources, respectively, are the first input bus of the first signal multiplier. multiplier, the gates of the second and third amplifying field-effect transistors are connected to the first terminals of the first and fourth adjustable sources of bias voltage, respectively, and are the second input bus of the first multiplier signal, the gates of the fifth and sixth amplifying field-effect transistors are connected to the first output of the sixth and fifth In addition, the controlled sources of bias voltage are, respectively, the first and second input buses of the second multiplier signal, the inputs control of the fifth and sixth adjustable bias voltage sources are connected to the reference voltage bus; the drains of the fifth and sixth amplifying field-effect transistors are connected to the inputs of the first and second current-voltage converters, respectively, whose outputs are connected to the combined control inputs of the first to fourth adjustable bias voltage sources, the drain of the first and third amplifying field-effect transistors through the first load resistor are connected to the first power bus, the drain of the second first and fourth field-effect transistors through the second load resistor are connected to the first power bus, which is connected to 45 50 55 Pa, the drain of which is connected to the second power bus, drains of the tenth and eleventh amplifying field-effect transistors and the drain of the twelfth amplifying transistor, the gate of which is connected to the first output of the fourth adjustable voltage source of conjugation, the second .-: The output of which is connected to the second output of the second an adjustable source of bias voltage and gate of the tenth field amplifying transistor, the source of which is connected to the sources of the second and twelfth amplifiers five Pa, the drain of which is connected to the second power bus, drains of the tenth and eleventh amplifying field-effect transistors and the drain of the twelfth amplifying transistor, the gate of which is connected to the first output of the fourth adjustable voltage source of conjugation, the second .-: The output of which is connected to the second output of the second an adjustable source of bias voltage and a gate of the tenth amplifying field-effect transistor, the source of which is connected to the sources of the second and twelfth amplifying field-effect transistors and the drain of the eighth amplifying field-effect transistor, the gate of which is connected to the second output of the second regulated voltage source, the first terminal of which is connected to the gate of the second amplifying field-effect transistor, the drain of which is connected to the drain of the seventh amplifying field-effect transistor and the control inputs of the first to fourth controlled voltage sources are connected to the output of the first current-voltage converter, the drain of the fourteenth amplifying field-effect transistor is connected to the station eye of the third amplifying field-effect transistor, the gate of which is connected to the first output of the 5th adjustable voltage source, the second output of which is connected to the gate of the thirteenth amplifying field-effect transistor, the source of which is connected to the sources of the third and fifteenth amplifying field-effect transistors and the source of the seventeenth amplifying field-effect transistor, the gate of which is connected to the first output of the seventh adjustable voltage source of the voltage, the second output of which is connected to the second The output of the third adjustable bias voltage source and gate of the fifteenth amplifying field-effect transistor, the drain of which is connected to the second power bus, drains of the sixteenth and seventeenth amplifying field-effect transistors and the drain of the eighteenth field-effect transistor, the gate of which is connected to the first output of the eighth adjustable voltage source an interface whose second output is connected to the second output of the fourth adjustable source of bias voltage and the gate of the sixteenth amplification of the role of the trazistor, the source of which is connected to the sources of the fourth and eighteenth amplifying field-effect transistors and the source of the fourteenth amplified field-effect transistor, the gate of which is connected to the second output of the sixth controlled voltage source, the first terminal of which is connected to the gate of the fourth amplifying field-effect transistor , the drain of which is connected to the drain of the thirteenth amplifying field effect transistor, and the control inputs of the fifth-eighth regulated voltage sources connected to the output of the second current transformer, the drain of the twentieth amplifying field effect transistor is connected to the drain of the fifth amplifying field effect transistor, the gate of which is connected to the first output of the ninth adjustable conjugate voltage source, the second output of which is connected to the gate of the nineteenth amplifying field effect transistor whose source is connected to the sources of the fifth and twenty-first amplifying field-effect transistors and the source of the twenty-third amplifying field-effect transistor, the P which is connected to the first output of the eleventh adjustable voltage source, the second output of which is connected to the second output of the fifth adjustable bias voltage source and the gate of the twenty-first amplifying field-effect transistor, the drain of which is connected to the first power supply bus, with the drains of the twenty-second and twenty the third amplifying field-effect transistors and the drain of the twenty-fourth amplifying field-effect transistor, the gate of which is connected to the first output of the twelfth regulated source nick voltage, the second output of which is connected to the second output of the sixth adjustable bias voltage source and the gate of the twenty-second amplifying field-effect transistor, the source of which is connected to the sources of the sixth and twenty-fourth amplifying field-effect transistors and the source of the twentieth amplifying field-effect transistor, the gate of which is connected to the second terminal of the tenth regulated voltage source of conjugation, the first terminal of which is connected to the gate of the sixth amplifying field-effect transistor and, a drain which are connected to the drain of the nineteen-nine amplified field-effect transistor, and the control inputs of the nine-twelfth controlled voltage sources are connected to the reference voltage bus, the drains of the second and third amplifying field-effect transistors are the first and second output multiplier buses. 2, The multiplier in ps, t t and - the fact that, from the first to the fourth, the controlled bias voltage sources contain every twenty-fifth n-type amplifying field effect transistor {twenty-sixth p-type amplifying field effect transistor and the first adjustable a source. the bias current, the gate of the twenty-fifth amplifying field-effect transistor being the first output from the first to the fourth regulated sources of bias voltage, the drain of the twenty-fifth amplifying field-effect transistor is connected to the first power line, and the source is connected to the source of the twenty-sixth amplifying field-effect transistor, the gate and drain of a co. are connected to the first output of the first controlled bias current source and are the second output from the first to the fourth regulated bias voltage sources, in The second conclusion is first-. A controlled bias current source is connected to a second power supply bus, and its control input is a control input from the first to fourth adjustable bias voltage sources. 3. The multiplier according to claim 1, of which the fifth and sixth adjustable sources of bias voltage each contain a twenty-seventh amplifying field effect transistor of p-type conductivity and a twenty-eighth amplification field effect transistor n- conduction type and a second adjustable bias current source, the gate of the twenty-seventh amplifying field effect transistor being the first terminal of the fifth and the sixth adjustable bias voltage sources, the drain of the twenty-seventh amplifying field-effect transistor is connected to the second power line, and its source is connected to the twenty-eighth source of the amplifying field-effect transistor, the drain and gate of which are combined with the first output of the second regulated bias current source and are the second output n the one and the sixth adjustable bias voltage sources, the second output of the second bias adjustable current source is connected to the first power supply bus, and its control input is are input and the fifth control the sixth regula prm sm. i OCHRLKOV 0 five 0 five 0 0 five 0 five 41 The multiplier is populated by the fact that, in order to increase accuracy over a wide range of temperatures, the first, second, fifth, sixth, eleventh, and twelfth regulated sources of conjugation voltage contain every twenty-ninth and thirtyth amplifying n-type zero-transistors, thirty-first and thirty-second p-type conductive field-effect transistors, and the first source of mating current, the gate of the twenty-ninth amplifying field-effect transistor being the first output of the first second second, fifth and sixth adjustable voltage sources and the second output of the eleventh and twelfth adjustable voltage sources, the drain of the twenty-ninth amplifying transistor is connected to the drain and gate of the thirty-first amplifying field-effect transistor and the gate of the thirty-second amplifying field-effect transistor, drain which is connected to the gate and drain of the thirtieth amplifying field effect transistor and is the second output of the first, second, fifth and 5th sixth regulated sources With the mating voltage and the first output of the eleventh and twelfth adjustable voltage sources, the sources of the twenty-ninth and thirtieth amplifying field-effect transistors are connected to the first output of the first adjustable current supply source, the second output, which is connected to the second power bus, and the control input is the control input of the first, second, fifth, sixth, eleventh and twelfth controlled voltage sources, and the sources of the thirty-first and thirty-second amplifier GOVERNMENTAL field transistors are connected to the first power rail. 5. An alternator according to claim 2, which is based on the fact that, in order to increase accuracy over a wide range of temperatures, the third, fourth, seventh, eighth, ninth and tenth regulated sources of interface voltage contain every thirty 15 the third and thirty-fourth conductive field-effect transistors, the thirty-fifth and thirty-sixth n-type conductive field-effect transistors, and the second regulated current source with a voltage, the gate of the thirty-third amplifying field effect transistor being the second output of the third, fourth, seventh and eighth of adjustable voltage sources of the conjugation and the first output of the ninth and tenth adjustable sources of voltage of the conjugation, the drain of the thirty third amplifying field transistor and connected to the drain and the gate of the thirty-fifth Nogo amplifier FET and a gate of the thirty-sixth amplifying FET, a drain of which is connected to the drain and gate tridem g 7822916 The four of the fourth field-effect transistor is the first output of the third, fourth, seventh and eighth controlled voltage sources and the second output of the ninth and tenth adjustable voltage sources, the sources of the thirty-third and thirty The IQ of the fourth amplifying field-effect transistors is connected to the first output of the second regulated current supply interface, the second output of which is connected to the first power supply bus, and 15, the control input is the control input of the third, fourth, seventh eighth, ninth and tenth controlled sources of current, and the sources of the thirty fifth and Two thirty-sixth amplifying output transistors are connected to the second power rail. 500 57 & 56 t -g 00 Г-О to YU 62 H Phage.2 75 81 -056 chz 86 85eML J Jfr. t I Jt iSvL, h Phage. five # 55 57 "G 78 "G 57 3 Phage. four FIG. 6