SU1474852A1 - Decoder - Google Patents

Abstract

The invention relates to telecommunications, computing, and can be used in digital data transmission systems in Manchester-2 code. The decoder automatically adjusts to the clock frequency of the input signal, which enhances the functionality of the decoder. The decoder has an input 1, triggers 2,5,6,10, element 3 NOT, elements 4,15 And, outputs 7,18, block 8 differentiation, element 9 OR, counters 11,14, registers 12,17, block 13 compare and a 16 clock pulse generator. 3 il.

Description

; b

fiv.1

The invention relates to telecommunications, computing and can be used in digital data transmission systems in Manshester-2 code.

The purpose of the invention is to expand the functionality of the decoder by automatically adjusting the change in the clock frequency of the input signal.

FIG. 1 shows a functional diagram of a decoder} in FIGS. 2 and 3 — timing diagrams explaining the operation and the principle of restoring the clock frequency of an encoder when decoding a signal with an 8-bit format.

The decoder (Fig. 1) has an input 1, the first trigger 2, the element NOT 3, the first element AND 4, the second 5 and the third one triggers, the first output ;; d 7, the differentiation unit 8, the element OR 9, the fourth trigger 10, the first a counter 11, a second parallel-write register 12, a block 13 of comparison, a second counter 14, a second element 15, a clock generator 16, a first shift register 17, and a second output 18.

The principle of operation of the decoder is based on the selection of information and clock pulses from the output signal with a specific format. The decoder measures half of the first clock signal interval and, using the measured value, reproduces pulses that coincide in frequency and phase with the clock pulses of the encoder.

The decoder works as follows.

If there is no input on input. 1, the decoder is reset. In this case, the output counter -14 blocks the trigger 10 at the R input and shuts down the comparison unit 13 at the control input. The first 2 and second 5 triggers are set to zero and are ready to receive information on the C-inputs. The zero signal from the direct output of the trigger 2 blocks And 4. The parallel register 12 is in the prohibitory recording state. The counter 11 sequentially counts on a negative front the pulses of the generator 16.

On fig.2a, b, c, the formation of a Manchester-2 code in the format of 8; bits in the encoder is shown. Single bit signal received in the first clock

0 „

0

with

0

interval, is the start bit. At time t0, the start bit of the code is fed to the input 1 of the decoder (Figure 2b and Over). The positive signal front overturns trigger 2 (Fig. 2k) and a single signal from its direct output goes to the second input of element 4. At the same time, a differentiated front of the signal through element 9 or 9 resets counter 11 to the zero state (Fig. 3b, d). The trigger 10 does not react to the signal at the C-input, as it is blocked by the signal from the output of the counter 14. The counter 11 starts counting the clock pulses (FIG. D, d) of the generator 16. At time t1, corresponding to half the clock interval, at the input 1 a low level is set which, through the NOT 3 element, does not open the AND 4 element. From the output of the AND element 4, a single signal (FIG. 10) allows the control input to write to the register 12, and also zero the counter 14. The output signal from the counter 14 (fig.2d) allows work on the S. -input trigger 10 and the input control laziness includes comparing unit 13. Register 12 on the positive edge of the clock pulse of the generator 16 rewrites the contents of the counter 1 1 (fig.Z3). By the same clock pulse, the comparator unit 13 generates an equal signal (FIG. Ze) of the output values of counter 11 and register 12. This signal, through the OR 9 element, twists the counter 11 and overturns the trigger 10 via the C input. A zero signal from the inverse trigger 10 closes the element AND 4. Thus, further writing to the register 12 is prohibited and the lock is removed from the counter 14 (Fig. 3).

The time position of the comparison signal is shifted by one clock of the frequency of the generator 16 relative to the clock edge of the encoder, but this discrepancy will not accumulate from the clock to the clock because the initial state of the counter 11 is periodically corrected by positive edges of the signal from the device bus. i

Thus, in register 12, a code is fixed, corresponding in the time domain to half the period of the encoder clock frequency. This code is stored until decoding is completed.

last bit of input information.

After zeroing with the comparison signal, the counter 11 starts a new counting from the moment of time t ,, (Fig. 3g). At time t2, the positive edge of the signal from input 1 passes, zeroing counter 11 and simultaneously triggering trigger 2 at the C-input (FIG. ZJ). In the following, this cycle is repeated. Counter 11 is zeroed by the positive fronts of the signal from input 1, and if there are none in the corresponding interval, then signals from the output of comparison unit 13.

On the C-inputs of the trigger 10 receives short pulses corresponding to the edges of the clock pulses of the encoder code Manchester-2 (Fig.2A, g). At the output of the trigger 10, the recovered encoder clock frequency is generated (Fig. 2e). From the output of the K-th bit of register 17 to the R-inputs of trigger 2 and

5, the recovered frequency is received, shifted by K-cycles of the frequency of the generator 16 (FIG. 2g).

These pulses permit the operation of triggers 2 and 5 only on the fronts located in the center of the clock interval. From the output of the AND 15 element, the output 18 receives synchronizing pulses (Fig. 2h) located in the middle of the decoded information pulses coming from the output of the triggers.

6 to exit 7 (FIG. 2m). The signal from the output of the trigger 6 corresponds to the original signal, with the exception of the start bit, which at output 7 goes to zero.

The counter 14 is filled with pulses from the inverse output of the trigger 10. After receiving the 8th pulse at its output at time tj,

Claims (1)

Claims of the Invention A decoder containing the first one - tre50 the HE is not, the clock input of the first trigger is combined with the input of the element NOT and is the decoder input, the output of the element is NOT connected to the clock input of the second trigger, the inverse is outputted by a single signal that blocks the trigger 10 for the R input and the input for the trigger I, control unit 13 comparison (fig.2d). After that, the decoder is ready to receive the next information packet, starting in the first clock cycle from a single start bit. The decoder allows you to adjust the formats of decoded data packets with a length of 4, 8, 16, 32, etc. bits. For this, the output of counter 14 is taken from the corresponding bits: 4, 8, 16, 32, and so on. The time diagrams (FIG. 3) show an example of measuring the clock the stroke of which is connected to the installation input to 1 of the third trigger and the information input of the first trigger, the inverse output of which is connected to the information input of the second trigger and the installation input to About the third trigger, the output of which is the first output of the decoder, ABOUT interval when the oscillator frequency 16 is 12 times the clock frequency of the original encoded signal a. However, for a confident decoder to work, it is necessary that F6 / F MOIKC 20, where F is the clock frequency of the generator 1 6; P, „p - maximum clock frequency of coding the signal. The lower frequency of the input signal is determined by the counter size 11 F-. Jl 5 "kn 2 n„ The dynamic range overlaid by the decoder is F D - F, s m  0.1 2 S mi for example, if Fu is 1 MHz, p 14, then G5 Meitt 50 kHz, F,  30 Hz. Thus, a decoder allows decoding signals from different objects at different distances and having different transmission rates. At the same time, there is no need for additional adjustments and switching. The decoder adjusts automatically to any clock frequency of the input signal from the overlapped dynamic range. In cases when, for some destabilizing factors, the generator of some encoder changes its frequency but continues to work, the decoder provides reliable decoding at the new frequency. Claims of Invention A decoder containing a first - three the ment is NOT, the clock input of the first trigger is combined with the input of the element NOT and is the decoder input, the output of the element is NOT connected to the clock input of the second trigger, the inverse of the trigger, the first element AND the stroke of which is connected to the setup input to 1 of the third trigger and the information input of the first trigger, the inverse output of which is connected to the information input of the second trigger and the installation input to About the third trigger, the output of which is the first output of the decoder, characterized in that, in order to expand the scope of the decoder by automatically adjusting to changing the clock frequency of the input signal, a differentiation unit, an OR element, counters, a clock generator, registers, a comparison block, a fourth trigger and a second element are entered into it And the block input differentiation is connected to the input of the decoder, the output of the differentiation unit is connected to the first input of the OR element, the output of which is connected to the installation input of the first counter and the clock input of the fourth trigger, forward The second output is connected to the information input of the first register, the output of which is connected to the first input of the second element AND and the installation inputs of the first if second trigger, the direct output of the first trigger is connected to the first input of the first element AND, the second input of which is connected to the output of the element HE, you 14748526 the stroke of the first element I is connected to the control input of the second register and the installation input of the second counter, the output of which is connected to the control input of the comparator unit and the installation input of the fourth trigger, the inverse output of which is connected to the third input of the first element I, the clock input of the second ten 15 20 the counter, the information input of the fourth trigger and the second input of the second AND element whose output is the second output of the decoder, the output of the clock generator is connected to the clock inputs of the first, second registers, the comparison unit and the first counter whose outputs are connected to the corresponding first information inputs of the block comparison and information inputs of the second register, the outputs of which are connected to the corresponding second information inputs of the comparison unit, the output of which is connected to the second Odom OR element. the stroke of the first element I is connected to the control input of the second register and the installation input of the second counter, the output of which is connected to the control input of the comparator unit and the installation input of the fourth trigger, the inverse output of which is connected to the third input of the first element I, the clock input of the second five 0 the counter, the information input of the fourth trigger and the second input of the second AND element whose output is the second output of the decoder, the output of the clock generator is connected to the clock inputs of the first, second registers, the comparison unit and the first counter whose outputs are connected to the corresponding first information inputs of the block comparison and information inputs of the second register, the outputs of which are connected to the corresponding second information inputs of the comparison unit, the output of which is connected to the second Odom OR element. Yanlyaya i I «-I 0 Sh I. I tim t 9 t f 3 to four .V / itf g