SU1474587A1 - Digital control system - Google Patents

Abstract

The invention relates to electrical engineering and can be used to stabilize the rotational speed of electric motors in automatic control systems. The purpose of the invention is to increase the speed of the system. The digital control system has a setting device 1, an adder 2, a reversible counter 3, a transducer 4 code-pulse duration, a power amplifier 5, a motor 6, the first decoder 7, element 8, the second decoder 9, a generator of 10 clock pulses, a speed sensor 11, a converter 12 period - code multiplexer 13. 1 Il.

Description

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The invention relates to electrical engineering and can be used to stabilize the rotational speed of electric motors in automatic control systems.

The purpose of the invention is to increase the speed of the system.

The drawing shows a block diagram of the system.

The digital control system includes the setpoint 1, the adder 2, the reversible counter 3, the transducer 4 code - pulse duration, power amplifier 5, motor 6, first decoder 7, element 8, second decoder 9, generator 10 clocks, speed sensor 11 converter period 12 - code and multiplexer 13.

The system works as follows.

From the output of the setting device 1, the input code H0 arrives at the first input of the adder 2, the second input of which receives the code N, from the converter 12 period - a code containing information about the speed of the engine 6. Information from the converter 12 period - the code arrives at the same time in the reverse code, t This means that the minimum code corresponds to the maximum speed, while the minimum code arriving from the setpoint device corresponds to the minimum speed. At the transfer output of adder 2, depending on which of the N0 or N signals is greater, a signal of a logical zero or a logical unit is formed: when N 0 N1, a signal of a logical unit is formed, and at N0 N1 a logical zero. The up / down counter 3 works respectively on addition at N0 -7 N and on subtraction at N., N6. At the output of adder 2, a code is formed that is equal to the NJ module of the difference N 4 JN 0 –N J codes. The N-i code is fed to the input of the second decoder 9, which, depending on the value of N4, generates a control signal to the multiplexer 13. The entire possible range of N is divided into n equal parts. Each part of the range has its own code at the output of the decoder 9, depending on which one or another frequency passes through the output of the generator of 10 clock pulses to the output of the multiplexer 13, at 0

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the larger the signal N7, the greater the frequency of the signal fed to the clock input of the reversible counter 3 through the element And 8.

At N0 N1, the reversible counter 3 works on addition, its code grows, and the clock frequency fed to the clock input of the counter, the larger, the larger the signal N2. At the output of converter 4, the code is the pulse duration, a pulse-width signal is generated through the power amplifier 5 to the motor 6. The pulse frequency is determined by the frequency of the generator output 10 clock pulses, and the duration is proportional to the code of the reversible counter 3, t That is, as the code of the reversible counter 3 increases, the pulse duration at the output of the converter 4 increases proportionally - the pulse width, and the motor 6 begins to accelerate.

With a wide range of stabilized speeds, situations may arise when N0 N, or N1 N0. For N 0 5 N1, the maximum code can be written into the reversible counter 3. In this case, the output of the first decoder 7 generates a logical zero signal, closes the 1st element AND 8, with the result that the next pulse from the multiplexer 13 does not pass to the clock input of the reversible counter 3 and the counter 3 does not overflow.

As soon as N1 is greater than M0, at the output of the first decoder 7 a signal of the logical level is generated | units, which opens the element of both 8, and the pulses from the multiplexer 13 are fed to the clock input of the reversible counter 3. The counter is working for subtraction. With N., N0 in the reversible counter 3, the minimum code can be recorded. In this case, the first decoder 7 formed by the output of a logical zero signal again closes the AND 8 element and does not transmit the next pulse to the clock input of the reversible counter 3 from multiplexer 13.

The course of the reversible counter 3 does not change abruptly from the minimum to the maximum, and the formation of the transition process is achieved due to

the fact that, for a larger value of the signal Na, the clock input of the reversible counter 3 receives a higher frequency.

With a small value of N g, a lower frequency arrives at the reversible counter 3, which, by virtue of the ability to often compare, on the adder N0 and N values, due to the use of the 12th period converter in the system, reduces the overshoot.

Claims (1)

Invention Formula Digital control system containing a setting device, serially connected converter code - pulse duration, power amplifier, motor and speed sensor, clock generator, the output of which is connected to the clock input of the converter code - pulse duration, reversible counter, clock input of which is connected to the output of the And element , and code output - with informational input transformed0 five 0 five Body code - pulse duration, characterized in that, in order to increase system speed, the first and second decoders, adder, period converter - code and multiplexer, whose data inputs are connected to a group of clock pulse outputs, are entered into it, and a control input through the second decoder connected to the information output of the adder, the first input of which is connected to the output of the setter, the second input through the converter period - the code is connected to the output of the speed sensor, and the output transfer connect ene to a signed entry down counter and to the first input of the first decoder, the second input of which is connected to the output of the transfer down counter, and a third input connected to the code output of down counter, a first input of the element and connected to the output of the first decoder and the second input - to the output of the multiplexer.