SU1467738A1 - Frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase speed. Frequency synthesizer contains accumulator adder 1, adder 2 codes, memory blocks 3 and 9, D / A converters 4, 10 and 16, adjustable amplifiers 5 and 11, low pass filters 6 and 12, multipliers 7 and 13, adder 8, shaper T4 quadrature signals and the shaper 15 of the code of the signal of cocktail, In the frequency synthesizer, by introducing the corresponding amplitude-phase manipulation of the signals at the outputs of the filters 6 and 12, the transient processes are localized at a given compensation interval, which increases its speed. The synthesizer of Claim 2 is characterized by the performance of shaper 15; given it silt. 1 hp f-ly, 2 ill.

Description

cash. Sc (t) Cos4wt and Ss (t) Sinda) t. At the output of the adder 8, a single band signal is formed.

S j ,,, (t) -and 6 ,, Cos () t + ZM l,

The former 14, the first and second multipliers and the adder 8 form in FIG. 2 — an example of the formation of a quadrature modulator. For locale, the Invention relates to radio engineering and can be used in radio communications, radar, to form a discrete frequency grid.

The purpose of the invention is to increase speed.

Figure 1 shows a structural electrical circuit of a frequency synthesizer;

Code of compensation signal codes.

The frequency synthesizer contains a nakakshi- vacant adder (NS) 1, adder 2 codes, first memory block 3, first digital-to-analog converter (DAC) 4, first adjustable amplifier 5, first low-pass filter 6, first multiplier 7, total 8j second block 9 the memory, the second DAC lOj the second adjustable amplifier 11 the second low-pass filter 12, the second multiplier 13, the shaper 14 quadrature signals, the shaper of the compensation signal t5 codes and the third DAC 16. The shaper 15 of the codes includes the first memory register 17 second reg mp 18 memory, AND gate 19, a counter 20, decoder 21, RS-trigger 22, a first block of nonvolatile memory (PSB) 23, and the second PPO 24

The frequency synthesizer works as follows.

At the initial time in NS 1, the zero frequency code K jf is written to the first register 17 and the second register 1B. A binary code of the required frequency is then fed to the first input of the frequency synthesizer, which is stored in the HC 1 B HI-S code of HC 1 by a synchronization pulse. the argument N of samples of the trigonometric functions Cos (21in / H) and Sin (21Tp / H), stored in the first and second memory blocks 3 and 9, respectively, where n is the order of the sample number, n 0.1, 2,.,. , H-1. The increment code of the argument code of trigonometric functions is 21K, 7H. With the release of the National Assembly 1 code argument

fi h, about the output of the ment through the adder 2 codes arrive at the address inputs of the first 3 and second 9 memory blocks, at the outputs of which samples of trigonometric functions are formed. Using the first 4 and second 10 D / A converters, these samples are converted into analog signals with a stepwise approximation, and with the help of the first 6 and second 12 filters, sig

When switching frequency at this interval, amplitude-phase modulation of the oscillations supplied to the first 6 and second 12 filters is carried out with the help of the first 5 and second 1t adjustable amplifiers at a given interval of transients that occur in the first 6 and second 12 filters.

R"

| A; {lIt- (i-t) (t-it)} Sin (Kfnt + /,)

t about t and t,

1 with SinKjSlt

at t - t

+ N + N

(2)

0

5 where A.

H 1 / f, N

five

Lee) 0

five

amplitudes at the outputs of the first 5 and second 11 control amplifiers; initial phases at the outputs of the first 5 and second 11 control amplifiers;

oscillation sampling interval; the order of the first 6 and second 12 filters; frequency shift of the output signal of the frequency synthesizer;

discrete frequency shift. The transient compensation interval is a multiple of the oscillation frequency of the clock frequency. The number of clock periods that make up the compensation interval is equal to the order of the first 6 and second 12 filters. At each i-M period of the oscillation of the clock frequency, a certain amplitude A is established in the compensation interval; and phase i /. signals to

51 21Г / Н;

the inputs of the first 6 and second 12 filters. The law of change of A values; and W (in the compensation interval for a given filter depends on the previous and set values of the frequency of the generated oscillation.

In order to provide the amplitude-phase modulation of the oscillations with the necessary parameters in the compensation interval, the frequency code K {is written to the first register 17 of the driver 15 codes. The initial clock pulse 20 is set to the zero state, the output RS-flip-flop 22 is set to the logical 1 state, which allows the clock pulses to pass through the AND 19 element to the counting input of the counter 20, using two groups of address codes from the first 17 and second 18 registers supplied to the address inputs of the first 23 and second 24 BNP, the required laws of phase and amplitude modulation of signals at the outputs of the first 4 and second 10 DACs are selected. The instantaneous values of the required phase shift (. Are selected from the second BZP 24, and the instantaneous amplitude values A. are selected from the first BPS 23 in the lower address bits, starting from the output of the counter 20.

Readable from the second PPC 24 codes c. arrive at the second input of the adder 2 codes, with which the phase modulation is carried out. With the release of the first BIS 23 amplitude codes A; are fed to the third D / A converter 16, where they are converted into an analog signal, with which the transmission coefficients of the first 5 and second 11 adjustable amplifiers are synchronously controlled. The number of A, and i, values required for full compensation of transients in the first 6 and second 12 filters is equal to the order of these ,, filters. Transients completely end up at the expiration of the compensation interval. The parameters of the first compensating pulse A, and t /, are selected from the first 23 and second 24 BNPs with a zero code from the counter 20 output. After passing to the counting input of the counter 20 of the first clock pulse from the first BOOP 23, the parameters of the second compensation pulse A are selected, and from the second BEP 24 - parameters of the second impulse compensation h, etc. After

sampling of the parameters of the n-r6 compensation pulse, the next clock pulse sets at the output of the counter 20 a code of the number n, which is decoded by the decoder 2t. The impulse from the output of the decoder 21 sets the RS flip-flop 22 to the zero state, and further passing of the clock JQ pulses through the AND | 9 element is prohibited. The impulse from the output of the decoder 2t, the contents of the first register .17 is entered into the second register 18. By any number of the first 17 and second T8 registers from the output of the first BOOP 23, the unit code is read in any states of the first 17 and second T8 registers. the transmission coefficient A, the first 5 and second P adjustable amplifiers, and the output of the second BFP 24 — the zero code of the phase Lff ,,. This ensures the formation of signals S (t) and SsCt) at the outputs of the first 6 and second 12 filters before recording 5 frequencies of the new frequency code into the synthesizer.

Thus, by introducing the appropriate a-minute-l () h) manipulation of the signals at the outputs of the first 6 and second 12 filters, localization of transients occurs at a given compensation interval, which increases the speed of the frequency synthesizer.

35

0

five

0

Claims (1)

Formula invention t. Frequency synthesizer containing accumulating adder, serially connected first memory block and first digital-to-analog converter, serially connected second memory block and second digital-to-analog, logic converter, serially connected first low pass filter, first multiplier and adder, serially connected second filter a low pass and a second multiplier, the output of which is connected to the second input of the adder, as well as a quadrature driver, the input of which is input m high frequency synthesizer, and the first and second outputs of the quadrature component generator are connected respectively to the second inputs of the first and second multipliers, while the clock, clock and code inputs of the accumulating adder are respectively clock