SU1462348A1 - Processor for performing operations with unclear sets - Google Patents

Abstract

The invention relates to computing technology and is intended for use in information and advising systems, on-line control of technological processes, as well as fuzzy logic controllers implementing fuzzy control algorithms and real-time operation. The purpose of the invention is to increase the productivity of a process by reducing the selection of operands. The goal is achieved by the fact that the processor containing the register 2, the comparison circuit 4, the first 3 and second 5 switches, the group 7 of elements I, the block 6 of the control memory, the counter 8. and the element 10 also entered an associative memory 1, which allowed to reduce the sampling time of the processed operands. 7 il. 0

Description

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Claims (1)

Claim A processor for performing operations on elements of fuzzy sets, comprising a register, a comparison circuit, 30 first and second switches, a group of AND elements, a control memory unit, a counter and an AND element, the first input of an AND element connected to a processor clock input, the output of an AND element connected to counter input of the counter, the output of which is connected to the address input of the control memory unit, the input, record of the counter is connected to the write input of the control ₄₀ memory unit and the input of the processor operating mode setting, the information input of the control unit The memory is connected to the input for loading the processor programs, the information input of the counter is connected to the ₄₅ input of the address of the processor micro-command, the direct output of the register is connected to the first information input of the first switch, the second information input of which is connected to the θθ version output of the register, the first, information output of the first commut -, the torus is connected to the first information on the input of the second switch and the first input of the comparison circuit, the second input of which is connected to the second information output of the first switch and the second information input of the second switch, the information output of the second switch is connected to the information input of the register, the second input of the AND element is connected to the first inputs of the AND elements of the group and the output of the end indicator. operation of the control memory unit, the second inputs of the AND elements are connected to the corresponding bits of the information the output of the second switch, the outputs of the elements AND groups form the output of the processor result, the first control input of the second switch is connected to the output of the operation code of the control unit memory, the second control input of the second switch is connected to the output of the comparison circuit, the control input of the first switch is connected to the output of the sign of the first operand and the output of the sign of the second operand of the control memory block, the input of the register record is connected to the output of the sign of the second operand of the control memory block, characterized in which, in order to increase productivity by reducing the sampling time of operands, is introduced into it. an associative storage device, wherein the information input of the associative storage device is connected to the information output of the second switch and the input of the initial values of the processor, the output of the associative storage device is connected to the third information input of the first switch and the register information input, the sign attribute of the associative storage device is connected to the output sign of the first operand and the output of the sign of the result of the control memory block, the output of the sign of the result of the block ulation memory coupled to the register write access, read-write input · invariant. formations, the output control input, the attribute recording inputs and the reset inputs of the matching triggers of the associative storage device are connected to the corresponding outputs · setting the control block mode. 16 17 FIG. 2 19 -> 20 - ’> eleven 12 21 22 • · · · 2 * • • * and 12 • · · · 1 TO FIG. At -1462348 00 cop Recognized 1 Sign 2 Sign of Result The number of cycles ko-, pandas 34 35 36 37 38 39 FIG. 5 01 cop Sign 1 Sign 2 Sign of Result 40 41 42 43 44 l • FIG. 6 10 cop Sign to 45 46 47 48 FIG. 7