SU1450129A1 - Demodulator of phase-manipulated signals - Google Patents

Abstract

The invention relates to telecommunications engineering and can be used in data transmission systems. The purpose of the invention is to increase the reliability of reception by reducing the likelihood of error. The demodulator contains a phase detector 2, a frequency multiplier of 3, amplifiers-formers 9 and 6, differentiating units 7 and 10, trigger 8, counter It, and r-th L2 pulses. element 13. In order to achieve the goal, a delay unit 1, a filter 4 and a phase shifter 5 are introduced into the demodulator. Filter 4 ensures that only the signal of the double carrier frequency passes, which provides an increase in the signal-to-noise ratio. Phaser 5 compensates for the phase shift of the signal during its processing in the circuit; amplifier shaper 9, differentiating unit 10, counter 11, element I 13. Delay unit 1 delays the input signal by the time it is processed in the circuit: multiplier 3, filter 4, phase shifter 5, amplifier shaper 6, differentiating unit 7, trigger 8. The de-modulator circuit is selected with such a condition that at the moment of the occurrence of an overflow pulse at the output of the trigger 8 there is always a low amusing, which corresponds to the reference oscillation. 1 il. (L

Description

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The invention relates to telecommunications technology and can be used in data transmission systems.

The purpose of the invention is to increase the reliability of reception by reducing the likelihood of an error.

The drawing shows a structural electrical circuit of the proposed demodulator.

The demodulator contains a delay unit 1, a phase detector 2, a multiplier of 3 frequencies, a filter 4, a phase rotation. 5, the second amplifier-shaper 6, the first differentiating unit 7, the trigger 8, the first amplifier-shaper 9, the second differentiating unit 10, the counter 11, the generator-I torus 12, the element And 13.

The demodulator of the phase-shift keyed signals operates as follows.

Let an arbitrary sequence of phase-shift keyed signals arrive at the input of the demodulator. At 10

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The second input of the phase detector 2 receives an information phase-manipulated signal, which is delayed in block 1 of the delay. The delay unit 1 holds the input signal for the time it is processed in the circuit: multiplier 3 - filter 4 - phase shifter 5 - amplifier shaper 6 - differentiating unit 7 - trigger 8.,. Parallel to the frequency multiplier 3, the input signal is fed to the input of an amplifier-former 9, which generates trapezoidal pulses. These pulses enter the differentiating unit 105 which ensures the separation of the front and rear edges of the pulses. Short pulses from the output of the differentiating unit 10 are fed to the R input of counter 11. The counting input of the counter receives pulses from the output of the generator 12 pulses. Clock and oscillator frequency 12 is much greater than the clock frequency

During the multiplier, 3 frequencies are formed by 25 demodulations. Counter i1 gives a signal pulse with double frequency. Frequency multiplication is a multiple of the modulation index, therefore at the output of multiplier 3, there will be a single phase signal. Filter 4 allows only 30 times the carrier signal to pass, which provides an increase in the signal-to-noise ratio,

I Next, the signal enters the phase switch 5, which compensates for the shift jj

; phase of the signal during its processing in

 amplifier circuit shaper 9, differentiation unit 10, counter 11, element 13.

From the output of the phase shifter 5, the signal reaches the input of the amplifier-former 6, which forms a sequence of positive pulses with clearly defined front and rear edges.45

The resulting sequence of pulses goes to the input of differentiating unit 7, which ensures the separation of the fronts of these pulses.

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Short pulses from the output of differentiator 7 arrive at the first input of trigger 8. Trigger 8 divides the frequency of the incoming pulses by 2 and forms a reference oscillation, which from its output goes to the second input of phase detector 2.

overflow only if the number of pulses from generator 12 turns out to be more than they can be received in one half-period of the information signal. This can occur when a phase change occurs in the information signal.

Thus, an overflow signal at the output of counter 11 appears at the moment of a change in the phase of the input fa-3 manipulation signal.

The overflow pulse from the output of the counter 11 is fed to the first input of the AND element 13, which compares the reference pulse from the output of the trigger 8 and the overflow pulse. At the moment of coincidence of these pulses, the output signal from the AND 13 element zeroes the trigger 8, the phase of the reference oscillation changes to 18C. The demodulator circuit is selected with such a condition that at the time of the appearance of the overflow pulse at the output of the trigger 8 there is always a low potential, which corresponds to the reference oscillation.

Claims (1)

Invention Formula A demodulator of phase-shifted signals, containing an element I, a phase detector, a frequency multiplier, the input of which is connected to the input of the first (first) amplifier of the former and is the input of the demodulator, The second input of the phase detector 2 receives an information phase-manipulated signal, which is delayed in block 1 of the delay. The delay unit 1 delays the input signal at the time of its processing in the circuit: multiplier 3 - filter 4 - phase shifter 5 - amplifier-driver 6 - differentiating unit 7 - trigger 8.,. Parallel to the frequency multiplier 3, the input signal is fed to the input of an amplifier-former 9, which generates trapezoidal pulses. These pulses enter the differentiating unit 105, which ensures the separation of the leading and trailing edges of the pulses. Short pulses from the output of the differentiating unit 10 arrive at the R-input of the counter 11. At the counting input of the counter, pulses come from the output of the generator 12 pulses. Clock and oscillator frequency 12 is much greater than the clock frequency demodulation. Counter i1 gives a signal overflow only if the number of pulses from generator 12 is greater than they can be received in one half-period of the information signal. This can occur when a phase change occurs in the information signal. Thus, an overflow signal at the output of counter 11 appears at the moment of a change in the phase of the input fa-3 manipulation signal. The overflow pulse from the output of the counter 11 is fed to the first input of the AND element 13, which compares the reference pulse from the output of the trigger 8 and the overflow pulse. At the moment of coincidence of these pulses, the output signal from the AND 13 element zeroes the trigger 8, the phase of the reference oscillation changes to 18C. The demodulator circuit is selected with such a condition that at the time of the appearance of the overflow pulse at the output of the trigger 8 there is always a low potential, which corresponds to the reference oscillation. Invention Formula A demodulator of phase-shifted signals containing the I element, a phase detector, a frequency multiplier, the input of which is connected to the input of the first amplifier of the former and is the input of the demodulator, the second power amplifier is connected to the first input of the phase detector, the first differentiator, the second input of which is the first block and the trigger, the second differential input of the element I is connected to the output of the citing block, the output of which is the trigger, the second the input of which is connected to the first input of the counter, the second one with the output of the element I, the second input of which is connected to the output of the generator which is connected to the output of the pulse counter, I distinguish that the output of the frequency multiplier is higher follower When the reception reliability filters are connected by a ui phase shifter is connected to the error probability input input terminal, the second amplifier amplifier, the delay unit, filter, and the phase amplifier of the first amplifier former are connected to the second input amplifier the differential is connected to the input of the demodulator and the high-power unit.