SU1446631A1

SU1446631A1 - Device for linear interpolation

Info

Publication number: SU1446631A1
Application number: SU874248644A
Authority: SU
Inventors: Владимир Павлович Власов; Михаил Алексеевич Мариненко; Владимир Александрович Васильев; Олег Викторович Воротынский
Original assignee: Ленинградский электротехнический институт им.В.И.Ульянова (Ленина)
Priority date: 1987-04-07
Filing date: 1987-04-07
Publication date: 1988-12-23

Abstract

Изобретение относитс к вычислительной технике и может быть использовано в устройствах восстановлени сигнала по отсчетам. Цель изобретени - повышение помехоустойчивости и степени фильтрации шумов. Устройство содержит блоки пам ти 1-4, сумматоры 5-7, блок.сравнени 8,блок 9 определени среднеквадратического отклонени , блок 10 определени степени сглаживани , блоки умножени 11, 12, блок вычитани 13, переключатель 14 и генератор 15 синхроимпульсов. Интерпол ционные оценки вычисл ютс в виде суммы предьщущей оценки и поправки, вычисленной с учетом нового входного значени и коэффициента сглаживани , тоже вычисл емого на каждом шаге 2 ил. а (Л :&amp; ОдThe invention relates to computing and can be used in signal recovery devices based on readings. The purpose of the invention is to improve the noise immunity and the degree of noise filtering. The device contains memory blocks 1-4, adders 5-7, block 8, block 9 for determining the standard deviation, block 10 for determining the degree of smoothing, multiplying blocks 11, 12, block for subtracting 13, switch 14 and sync pulse generator 15. The interpolation estimates are calculated as the sum of the previous estimate and the correction calculated with regard to the new input value and the smoothing factor, also calculated at each step of 2 or more. a (L: & Od

Description

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Изобретение относитс к вычислительной технике и может быть использовано в устройствах восстановлени сигнала по отсчетам,.The invention relates to computing and can be used in signal recovery devices based on readings.

Цель изобретени - повьшение помехоустойчивости и степени фильтрации шумов.The purpose of the invention is to increase the noise immunity and the degree of noise filtering.

На фиг. 1 представлена схема устройства; на фиг. 2 - конструкци / Ю арифметического блока.FIG. 1 shows a diagram of the device; in fig. 2 - arithmetic unit / S block.

Устройство содержит блоки 1-4 пам ти Сс первого по четвертый), первый 5, третий 6 и второй 7 сумматоры, . блок 8 сравнени , блок 9 определени is среднеквадратического отклонени , блок 10 определени сглаживани , первый и второй блоки 11 и 12.умножени , блок 13 вычитани , переключатель 14, генератор 15 синхроимпульсов. Блок 20 10 определени степени сглаживани содертит (фиг. 2) первый и второй вы- читатели 16 и 17, первый и второй перемножители 18 и 19,. четвертый и п тый сумматоры 20 и 21, п тый и шестой 25 блоки 22 и 23 пам ти, блок 24 определени модул , блок 25 делени .The device contains blocks 1-4 of memory Cc first to fourth), the first 5, the third 6 and the second 7 adders,. a comparison unit 8, a standard deviation determination unit 9, a smoothing determination unit 10, first and second multiplication units 11 and 12. multiplication, subtraction unit 13, switch 14, clock generator 15. The degree of smoothing unit 20 10 will contain (Fig. 2) the first and second recievers 16 and 17, the first and second multipliers 18 and 19 ,. the fourth and fifth adders 20 and 21, the fifth and sixth 25 memory blocks 22 and 23, the module determining unit 24, the division unit 25.

Устройство работает следующим об- разом.The device works as follows.

Отсчеты сигнала х; поступают, на 30 |вход с периодом т; Рассчитанное в блоке 9 среднеквадратическое отклонение очередного отсчета от среднего значени сравниваетс в блоке 8 сравнени с разностью их ; х; - х, , 35 где оценка процесса, полученна на предыдущем шаге и хран ща с в блоке 4 пам ти. .Большее из сравниваемых значений поступает на вход блока 11 уьшожени , где умножаетс 40 на показатель сглаживани d, рассчитываемый в блоке 10 по формулеSignal counts x; arrive at 30 | entry with a period of t; The standard deviation of the next sample from the average value calculated in block 9 is compared in block 8 comparison with their difference; x; - x,, 35 where the process estimate obtained in the previous step and stored in memory block 4. The larger of the compared values is fed to the input of block 11 of the output, where 40 is multiplied by the smoothing index d, calculated in block 10 by the formula

о{, „ a ±JiIu5iw lJL|il &х; + оССлхи, - лх;) o {, „a ± JiIu5iw lJL | il &x; + oSSlhi, - lh;)

где оС - коэффициент передачи; UK; - оценка нев зок; . i x . - оценка модулей нев зок, т.е. той доли разности uxj, которую надо прибавить к оценке п процесса, полученной .на пре- дццущем шаге.where оС - transfer coefficient; UK; - Nevzok assessment; . i x. - modulus estimation module, i.e. that fraction of the difference uxj, which must be added to the estimate n of the process obtained at the previous step.

В сумматоре 7 вычисл етс очередна оценка процесса как сумма предыдущей оценки и произведени о(.ЛХ;, котора поступает на выход и запоминаетс в блоке 2 пам ти, причем значение , хранившеес в блоке 2, предварительно переписываетс в блок 3 па .In adder 7, the next process estimate is calculated as the sum of the previous estimate and product o (.LH; which is output and stored in memory block 2, and the value stored in block 2 is pre-written in block 3 pa.

s 0 5 s 0 5

0 5 0 0 5 0

5five

п P

м ти. Их разность, вычисл ема блоком 13 вычитани , задает коэффициент роста. Сумма xj , полученна на выходе сумматора 6, вл етс прогнозом процесса на один шаг вперед; После перезаписи в блоке 4 она используетс дл сравнени со следующим отсчетом.mi ti Their difference, calculated by subtractor 13, sets the growth factor. The sum xj obtained at the output of the adder 6 is a one step forward process prediction; After being overwritten in block 4, it is used for comparison with the next reading.

Claims

Apparatus of the Invention A linear interpolation apparatus comprising a first memory block, whose information input is an input of a device, a clock generator, the output of which is connected to a control input of a first paramotor unit, an output of which is connected to the first input of the first adder, the first multiplication unit, a comparator unit, a subtraction unit and a second memory unit, characterized in that, in order to improve the noise immunity and the degree of noise filtering, the device comprises a unit for determining the standard deviation, the second multiplication unit, the third and fourth memory blocks, the second and third adders, the switch and the smoothing degree determination block containing two subtractors, two multipliers, the fourth and fifth adders, the fifth and sixth memory blocks, the module definition and the dividing unit, the input of the device is connected to the information input of the unit for determining the standard deviation, the synchronization input of which is connected by the clock generator, and the output is connected to the first information input of the switch and The first input of the comparison unit, the output of the first adder is connected to the second information input of the switch and the second input of the comparison unit, the output of which is connected to the control input of the switch, the output of which is connected to the first input of the first multiplication unit, as well as to the first input of the first subtractor of the smoothing degree determination unit, the output of the division unit, which is the output of the smoothing degree determination unit, is connected to the first input of the second multiplication unit and to the second input of the first o the multiplication unit, the output of which is connected to the first input of the second adder, the output of which, being the output of the smoothed process estimate, is connected to the information input of the second memory block, the output of which is connected to the information input of the third memory block and to the first inputs of the third adder and a subtraction unit, the second input of which is connected to the output of the third memory block, which is the output of interpolated process values, the output of the subtraction unit is connected to the second input of the second multiplication unit, the output of which This is connected to the second input of the third adder, the output of which is connected to the information input of the fourth memory block, the output of which is the output of the block for determining the degree of smoothing of process values, is connected to the second inputs of the first and second adders, the output of the subtractor, the outputs The first and second subtractors are connected to the first inputs of the first and second multipliers, the second inputs of which are connected to the coefficient setting bus, and the outputs to the first inputs of the fourth and fifth co-actuators Respectively, the outputs of which are connected to the information inputs of the fifth and sixth memory blocks and the inputs of the divisible and divider blocks, dividing, the output of the fifth memory block is connected to the second inputs of the first subtractor and the fourth adder, the output of the sixth memory block is connected to the second inputs the second subtractor and the fifth adder, controlling the inputs of the second, third, fourth, fifth, and sixth memory blocks, are connected to the output of the clock generator.

FIG. 2