SU1444823A1 - Arrangement for determining characteristics of random processes - Google Patents

Abstract

The invention relates to specialized computer aids and is intended to determine random process quantiles (SPs). The purpose of the invention is to increase speed and increase functionality by providing the ability to analyze non-stationary random processes. The device contains a t-shift register with a volume of N + 1 bits, a group of blocks for generating order statistics, a group of blocks of bus drivers, a group of interpolations, a block of code comparison, a clock generator A block of forming order statistics contains a register, two comparators, a switch code, two AND element, three elements EXCLUSIVE OR, two elements OR “. The n-shift register is entered into N g-bit readings of the SP measurements in the order of their arrival at the device input, and the registers contain the order statistics of this set of measurements. The values of the codes recorded in the registers arriving at the outputs of the device with known numbers are quantized joint ventures. The other outputs of the device contain quantiles, the values of which are not determined as exact values of the order statistics, but are calculated by interpolation. Upon receipt of the next reference point SP (X), the device for three clock cycles of the clock generator determines the values of quantiles dp of the analysis interval. The earliest measurement (X) is excluded from the analysis. 1 hp f-ly, 2 ill. § (L (ib 4 4 OS 1C 00

Description

The invention relates to specialized means of computer technology and can be applied in determining the statistical characteristics of random variables, namely, in determining quantiles with an arbitrary unknown random distribution; quantities

The aim of the invention is to increase the speed and enhance the functionality by enabling the analysis of a non-donor random process.

Fig about 1 presents a block diagram of the device; in fig. 2 is a block diagram of the order statistics generation unit.

The device contains a t-shift 1 register, input 2 of which is

information input of the device, a group of order statistics statistic units 3, the first and second information inputs of which are connected respectively to the outputs of the first

and (N + 1) -x bits of the tp-shift register 1 and with the first and second inputs of block 4 of code comparison, bus drivers 5, the inputs of which are connected to information outputs of blocks 3 of GROUP; and the outputs are the first group of information outputs 6 of the device, a group of interpolation blocks 7, the outputs of which are the second group of information outputs 8 of the device, block 9 of the clock generator, the first output of which is connected to the control input of the tp-shift register 1. Information output The first block 3 is connected to the third information input of the second block 3 of order statistics generation, the information output ir of block 3 (1 2, N-1) is connected to the third information input (i + D-ro Oloka 3 and the fourth information input). input (r-1) -th block 3, information output of the last N-ro block 3 is connected to the fourth information input (N-1) -ro block 3 "The first control inputs of the formation unit of the order statistics of the group are connected to the output of block 4 comparing the codes, the second control inputs of the blocks 3 are connected to the third control input of the first block 3 and connected to the second output of the clock generator block 9. The unequal output of the first block 3 is connected to

Q

s

0

five

0 c 0 5

0

five

the third clock input of the second block 3, the unequal output of the i-ro block 3 (i 2, N-1) is connected to the fourth clock input (il) -ro of block 3 and the third clock input (i + 1) -ro of block 3, output unequalities of N-ro block 3 is connected to the fourth clock input (Nl) -ro of block 3, the fourth clock input N-ro block 3 is connected to the combined clock inputs of blocks 5 and connected to the third output of block 9 of the clock generator,

The order statistics generation unit 3 contains the first 10 and second 11 digital comparators, the first inputs of which are the first and second information inputs of the block respectively, and the second inputs are combined and connected to the output of the register 12, which is the information output of the block, the first 13, the second 14 and the third 15 elements EXCLUSIVE. OR, the first inputs are connected to the unequal output of the first digital comparator 10, which is the clock output of the block, the first 16 and second 17 elements AND, the first inputs of which are respectively the first and second clock inputs of the block, the first 18 and second 19 elements OR. The second input of the first element EXCLUSIVE OR 13 is connected to the output of the second 11 of the digital comparator 11, and its output is connected to the first input of the first element OR 18. The output of the second 1 1 digital comparator 11 is connected to the BTopbiM input of the first element And 16, the output of which is connected to the second input of the first element OR. The output of the first element OR 18 is connected to the second input of the second element AND 17, the output of which is connected to the input of the register 12. The outputs of the second t4 and the third 15 elements EXCLUSIVE OR are connected respectively to the first and second inputs of the second element SHI 19, and their second inputs are the third and fourth clock inputs of the block respectively. The first bit of the address input of the switch 20 codes is connected to the first input of the first element AND 16, and its second bit is connected to the output of the second element OR 19.

The device implements the following algorithm for determining quantiles.

the N-1 bit m-shift register contains N bits of measurements of a random process X; in the order of their arrival at the input 2, the device, ie, the number recorded in the Nx bits of the t-shift register 1 () corresponds to the count (measurement) of the random process at the beginning of the analysis interval (the oldest measurement), and the number recorded in the first bits of the t-shift register 1, corresponds to the measurement at the end of the analysis interval (the last current measurement). The number of bits N of register 1 determines the magnitude of the analysis interval, or sample size of the random process under investigation.

In registers 12 of block 3, codes of order statistics X are recorded; numbers stored in the t-shift register 1, (hereinafter, the samples of the random process sample are denoted by X-, where i is the bit number of the t-shift register 1, and the members of the ranked series of values are Xj where i is the member number of the ranked number (yes).

It is known that order statistics have such a property that the number of a member of the order statistics allows in advance, without knowing the specific value of this member and the type of distribution function of the random variable F (x,, it is sufficient to accurately estimate its corresponding value F (X.) P. by expression

F (xl) R. i / N + 1. eleven

Thus, the block numbers 3 and the code values in the registers 12 of these blocks provide all the necessary information to form quantiles.

Having predetermined the block numbers 3 registering the value of the codes in the registers 12 of these blocks, we get the values of the quantile PJ as the contents of my register 12 (i + 1) -ro of block 3, If the desired quantile is not determined as the exact value of register 12 of block 3, then more the exact value can be found by interpolating the values of the two nearest neighboring quantiles of the larger and smaller given

If the device enters the next countdown of the random

, -,

i

444823

process, it corresponds to the fact that the analysis interval has shifted one sample to the right and takes place. a new random process sample, different from the old one, replacing the Xy value with the new X value

20

25

thirty

35

40

45

50

55

U «« ilS.LJVJ about l K 1% L 111 J I

in the proposed device, the old value X (y goes to (Y + 1) -th time 10 p d t-shift register 1, i.e. the old X | j X, is excluded from the analysis and the new X is inserted.

You need a number to get a ranked number of this new sample.

15 order statistics of the old sample, the values of which lie in the interval LX ,, X f44. (L, increase by one for Xn, X, or decrease by one

at X, Hm.,. and on liberated pip.rg ranked rank yes

X value. The remaining members of the ranked number remain in their places.

In the proposed device, changing the numbers of the order statistics of the modified part of the ranked series is performed by simultaneously rewriting the values of the order statistics recorded in the registers of 12 blocks into adjacent blocks 3, i.e. The values are shifted by the order statistics values to the left or right. Having determined the vacant spaces in the ranked row, the value X is written to it. Using the communication logic of the elements of the blocks 3, these operations in the device occur in one clock cycle.

With the arrival of a new reference, the described operations are repeated, thus ensuring continuous measurement of the characteristics of a random process over a sliding measurement interval.

The device works as follows.

In the initial state, the codes of randomly selected N g-bit numbers are written in the t-shift register 1, and in registers of 12 blocks 3 there are order statistics of these numbers, in particular, these can be zeros. Before starting, the contents of the tn-shift - the first register T and the registers 12 of the blocks 13 are zeroed out (in Figs. 1 and 2, the zeroing chains are not shown).

The device works in three cycles.

During the first clock cycle, the clock pulse from the first output of the clock generator unit 3 arrives at the control input of the t-shift register 1 o. All samples are shifted one position to the right. Old value X | will appear in (N + 1) -x bits, and in the first bits the first count of the random process will be recorded.

After the first cycle of operation of the device, the first and second information inputs of blocks 3, which are the first inputs of the first 10 and second 11 digital comparators, enter the codes of numbers X, and Hz.,. Codes of the same numbers also arrive at block 4 of code comparison, the output of which forms a logical unit with

l U4.I X.

., L | and zero at x, o

In blocks 3, the X values, and X,

MOR N -. (

The steps for the first inputs of digital comparators 10 and 11 are compared with the order statistics stored in the registers 12 of these blocks IF their values satisfy the condition X, X-, X, or Xfj,: x. , then, at the outputs the inequality of the digital comparators 10 and 11, opposite logical levels are formed and, therefore, at the outputs of the first element EXCLUSIVE OR 13 of such block 3, a logical unit appears. For the remaining blocks 3, the output of this element will be zero o

During the second clock cycle, a clock pulse is sent to the second clock inputs of blocks 3 from the second output of the clock generator generator. For all blocks 3 that have a unit ON the output of the EXCLUSIVE IL 13, a logical one is outputted from the second element 17 recording the switch output of 20 codes into register 12. For case Xj, the same resolution of recording 6 and register 12 also appears in block 3, for which the values of X and X c are the same, since in this block 3 the output is equal to second qi rovogo comparator 11 (a second input of the second AND gate 17) and chains of the first discharge switch 20 input address codes (first input of the second AND gate 17) will be unity.

The type of circuit connected by the switch 20 codes to the information input of the record of register 12 of block 3 is determined by the code value to its address

 i

Nominal input The input circuits to the switch 20 codes are connected in such a way that when the address code is 00, it

g connects to the information input of the register entry 12 i-ro of block 3 informational output (i + 1) -ro of block 3 () Address code 01 connects to the information input

10 records of register 12 i-ro block 3 informational output (i-l) -ro block 3 (X |,), and with codes 10 and 11 the first bits of the t-shift register 1 are connected

15 The value of the first bit of the address code is generated by the code comparison unit 4 and is determined by the sign of the difference of magnitudes.

With Xfvji. (X, on block 4

20 code comparison is set to one, otherwise zero. The code value of the second bit is determined by the output level of the second element OR 19, which is the logical sum of the output levels of the second and third elements EXCLUSIVE OR 14 and 15. The presence of unity 1 at the output of the second element OR 19 in one of block 3 indicates that it

30 first, in which the sign has changed

difference X - X | (output of the first digital comparator 10). In total there may be two blocks 3 in which this is observed, since a change is fixed

35 characters when viewing a series of values from left to right and from right to left, but assuming that the enabling write level at the control inputs of registers 12 of block 3 appears when the conditions described above are met, the X code will be written into register 12 of only one block 3, after rewriting In registers 12 blocks 3 new code values ends the second cycle of operation of the mouth

45 roystva. A ranked row of new crotch has been formed.

Attaching the third clock input of the first block 3 to the second, and

the fourth clock input N-ro of block 3 to the third outputs of block 9 of the clock generator provides during the second cycle of the device the presence on them of units and zero, respectively, which allows you to correctly enter the new value of X in the ranked range, if the new value of Xf is the smallest or the largest for the new sample.

When a sync pulse arrives from the third output of the sync pulse generator block 9 to the clock inputs of the blocks 5, the order statistics of the sampling of the random process being studied are formed at the outputs of these blocks. The sought quantile values are found either directly from the outputs 6 with known numbers or after interpolation by blocks 7 from the outputs 8 o

With the arrival at the input of 2 t-shift register 1 of a new sample of a random process synchronized with the operation of block 9 of the clock generator, the cycle of generation of order statistics for the new set of sample values described in the input to the first output of the clock generator, a group of bus drivers whose outputs are the first group of information outputs of the device, the group of interpolation blocks, the first and second information inputs of each i-ro interpolation block (, 0 N-1) with (the corresponding With the i-ro and (i + 1) -ro outputs of bus drivers, the outputs of interpolation blocks are respectively the second group of information outputs of the device, the information input of the shearing

The register is an information input of the device, a code comparison unit, characterized in that, in order to increase speed and decrease, is repeated. After the arrival, 20 expansion of the functional capabilities of N counts in blocks of 3 forms due to the possibility of

order statistics, compilation of nonstationary random data from samples of the measured random process are drawn. At the output of the device, there are quantiles of a random process for the interval from 1

processes, a group of order statist formation units is introduced into it, the first and second informational inputs of which are connected to the outputs

448238

whose input is connected to the first output of the clock generator, a group of bus drivers whose outputs are the first group of information outputs of the device, a group of interpolation blocks, the first and second information inputs of each i-ro interpolation block (, 0 N-1) co ( connected respectively with the outputs i-ro and (i + 1) -ro bus drivers, the outputs of the interpolation blocks are respectively the second group of information outputs of the device, the information input is a shift

 analysis of non-stationary random

processes, a group of order statist formation units is introduced into it, the first and second informational inputs of which are connected to the outputs

up to N counts. After the arrival of the () -ro samples, the quantiles for the interval from 2 to N + 1 samples are found at the output of the device, i.e., the device measures quantiles moving along a real process of a random process by a sliding window

When determining the quantile of a random process, when the next sample arrives, the device needs to perform three operations on an interval of N samples, while the prototype needs an average of + N operations to build quantiles, t, e, the proposed device has a much higher speed. The equal number of operations during the processing of the next sample makes it easy to implement the real-time measurement mode. Continuous measurement of the characteristics of a random process using a sliding window makes it possible to measure the characteristics of non-stationary processes, which significantly expands the functionality of the device compared to the prototype.

Formula and

the acquisition of 55 all order statistic generation units and the third clock input of the first order statistic generation unit are combined and connected to the second generator output

Claims (1)

1 "Device for determining the characteristics of random processes, containing a shift register, clock the first and (N + 1) -ro bits of the shift register, connected respectively to the first and second inputs of the code comparison block, the information outputs of the order statistics group building blocks are connected respectively to the inputs of the bus drivers, the information outputs the course of the first order statistics generation unit is connected to the third information input of the second order statistics generation unit; the i-ro information output The order statistics generation unit (i 2, N-1) is connected to the fourth information input (i-l) -ro of the order statistics generation unit and the third information input (i + O-ro block of order statistics, information output of the last N-ro block of order statistics, connected to the information input of (N-l) -ro block ordering 1H statistics, the first clock inputs of the order statistics generation blocks are combined and connected to the outputs of the code comparison block, the second clock speed sync pulses, the inequality output of the first order statistics generation block is connected to the third clock input of the second order statistics generation block, the unequality i- output The ro statistic generation unit (i 3, N-1) is connected to the fourth clock input (il) -ro of the random statistics generation unit and to the third clock input. house 1 + 1) -th block form a sequence of statistics nonequivalence yield N-ro the output of which is connected to the first input of the first OR element, the first information input of the code switch is connected to the first input of the first digital comparator, the second and third information inputs of the switch are the third and fourth information inputs 10 of the block, the first address input of the code switch, which is the first .tact input of the block, connected to the first input of the first element, And, the second input of which is connected to the formation of the order statistics; 15th Equivalence of the second digit and is connected to a fourth clock input of (N-l) -ro block forming a sequence of statistics, a fourth clock input N-ro unit generating a sequence of statistics is combined with the clock inputs of the bus drivers, and is connected to a third output clock generator. 2o The device according to claim 1, of the compiler of the comparator, the second bit of the address input of the code switch is connected to the output of the second OR element, the output of the code switch is connected to the information input of the register, the recording control input of which is connected to the output of the second element And, the first input of the second element is the second clock input of the block so that the block is molded, the second input of the first element is AND The order statistic contains two digital comparators, three EXTENDING OR elements, two AND elements, two NL elements, a register, and a code switch, the first inputs of the first and second digital comparators being the first and second information inputs of the block, the second information inputs of which are connected with the register output, the information output of the block, the inequality outputs of the first and second digital comparators are connected to the first and second inputs of the first element EXCLUSIVE OR, 482310. the output of which is connected to the first input of the first OR element, the first information input of the code switch is connected to the first input of the first digital comparator, the second and third information inputs of the switch are the third and fourth information inputs 10 of the block, the first address input of the code switch, which is the first block input is connected to the first input of the first element I, the second input of which is connected to the comparator coupling, the second bit of the address input of the code switch is connected to the output of the second element OR, the output of the code switch is connected to the information input of the register, the recording control input of which is connected to the output of the second element AND, the first input of the second element AND is the second clock input and connected to the output of the first element OR, the second input of the first element OR is connected with the output of the first element And, the output of the first digital Comparator is connected to the first inputs of the second and third elements EXCLUSIVE OR, the outputs of which are connected to the first and second inputs of the second element OR, sec the second inputs and the third elements EXCLUSIVE OR are the third and fourth control inputs of the block respectively, the output of the first digital comparator is the clock output of the block. Well e.2 Compiled by L.Grigor n-reader Editor M. Tsitkina Tehred M. DidykKorrektor N. Korol eight Nt ii i 6-f-f