SU1444799A1 - System switching arrangement with priority servicing - Google Patents

Abstract

The invention relates to the field of computing technology and can be used to create computing systems. The purpose of the invention is to expand the field of application by providing software configuration when laying the switch channels and decentralized priority service. To achieve this goal, the system switch contains a switching unit that contains three elements of two-way conductivity and three software configuration blocks. 8 il.

Description

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The device relates to the field of computer technology and can be used to create computer systems.

The purpose of the invention is to expand the scope of use by providing software configuration when laying the switching channels and decentralizing priority service.

FIG. 1 is a functional diagram of the switch; in fig. 2 illustrates an exemplary use of the system switch j in FIG. 3 is a functional diagram of the control unit i in FIG. 4 is a priority decoder in FIG. 5 is a diagram of a control block for switching and the order of connecting thereto a program channel tuning unit j in FIG. 6 is a diagram of a channel software adjustment block; FIG. 7 is a control register memory node of FIG. 8 is a trigger circuit with auto reset circuit.

The system switch (fig. 1) is 25 ki 18). At the same time, the specified in the code is delivered by the switching unit 1, - the unit 2 of the pack-up unit 2 (block 18) will be occupied,

commuting, with block 1 containing three j elements of two

if there are no other simultaneous signals on line 17 for it. When simultaneously requesting

third-party conductivity, three program setting blocks 43, common buses 30 to free block 2 (block 18), it is 5, -5 о ,, lines of communication (tires), ob is occupied by a request for lines Disconnecting buses 7-9, buses 10 settings , switching control lines 11-16, sync line 17.

FIG. 2 shows the system m 11-16 to the inputs of the elements of the 3 switches, subscribers 19, the bus drive receives signals controlled by 20, including buses 6–9.

The switching control unit comprises a control unit 21 and a priority decoder. The control unit 21 40 of FIG. 3) contains elements OR 22-24, generators 25-27 of single pulses, elements OR NOT 28-30, elements OR 31-36, a group of elements AND 37, a group of triggers 38-43, a group of elements 45 in the following way. The initial state is 44-49, lines 501-50з, 3, the following: triggers 38-43 are reset,

 e, 53, -53з, 54, -54z, 56 1-56}, 57, -57-1, 58-60 communications.

The priority decoder 61 (FIG. 4) contains an OR-NOT 62 element, Q & A elements 63-65, communication lines 66, -66j. The program setting block (Fig. 6) contains a comparison circuit 67, the AND element

bus 10 with a higher fixed priority. At the same time, according to the setting from block 2

neither Through the elements 3, predetermined tire pairs are connected. Sequences of tuning steps form channels of busbars 5. When signal 1 is applied to lines 11-16 of element 3, data is allowed to pass through element 3 via K to bus lines 5. Operation of control unit 21 (Fig. 3) input signals 52, -52e signal ABOUT.

Sample bus 5 according to the signals from the bus 5, (at signals 1.56., 58 l 1 50) signal 1. from the element And 44 will set

trigger 38 into 1. Signal 1 from lines 11 will turn on element 3, -, and bus lines 5t, and 5 .J connect. Signal 1 from trigger 68, RS flip-flop 69, controlling regitrigger 38 in 1. Signal 1 from lin 11 will turn on element 3, -, and the bus lines and 5 .J will be connected. Signal 1 with trig

strovu memory 70, element AND-OR 71, 55 pa 38 through the elements AND 37, OR 32,

a decoder 72, counters 73, 74, a decoder 75, a comparison circuit 76, links 77-83, a reset input 84, links 85-96.

OR NOT 29 and OR 35 is applied to the lin 51, 50, 53l. Signal 1 with elements OR 32 through element OR 23, the generator 26 is transmitted to lily 54.

The control register memory (Fig. 7) contains keys 97.98, elements OR 99-101, elements AND 102, 103 triggers 104 ,, 105, elements And 106, 107, triggers 108, 109, one-shot 110, 111 , And 112, 113 elements, triggers 114-121, communication lines 122-129.

The trigger 114 may contain an auto-reset circuit. With this in mind, it may contain (Fig. 8) one-shot.

130, 131, elements And 132-135.

Proposed System Switch

works as follows (see Fig. 1.2).

Subscribers 19 of each tire 5, independently of each other, can bring using tires 7–9 (bus 20) into memory

Blocks 4 codes of channel setting and control steps. At the end of the recording, blocks 4 on buses 6 and 10 issue their first-step codes to settings on adjacent buses 5, 10 blocks 2 (there were no other simultaneous requests on line 17 for it).

 to free block 2 (block 18), it is occupied by a request for the Prerah lines, by free block 2 (block 18), it is occupied by a request to the line Bus 10 interruption with a higher fixed priority. At the same time, according to the setting from block 2

the mutator receives control signals

 in the following way. The original state: the triggers 38-43 are reset, on

neither Through the elements 3, predetermined tire pairs are connected. Sequences of tuning steps form channels from chains of buses 5. When signal 1 is applied to lines 11-16 of element 3, two-way data transmission is allowed through element 3 via K lines of bus 5. Control unit 21 (Fig. 3) operates as follows. The original state: the triggers 38-43 are reset, on

inputs 52, -52e signal O.

Sample bus 5 according to the signals from the bus 5, (at signals 1.56., 58 l 1 50) signal 1. from the element And 44 will set

trigger 38 into 1. Signal 1 from lines 11 will turn on element 3, -, and bus lines 5t, and 5 .J connect. Signal 1 from trigger 38 via AND 37, OR 32 elements,

ra 38 through the elements AND 37, OR 32,

OR NOT 29 and OR 35 appear on line 51, 50, 53l. The signal 1 from the element OR 32 through the element OR 23, the generator 26 is transmitted to the lily 54. The pulse,

will go through line 54 to element 3, line 54 - to the counting input of counter 73 of block 4. When sampling bus 5j according to the settings signals from pin 5, (with signal signals 1 57, l O 58, A 1 5f. signal 1 from the output of element And 45 will set the trigger 39 to 1. Signal 1 on line 13 will turn on element 3j, and bus lines 5, and 5, connect mc. Signal 1 from trigger 39 through, elements AND 37, CRT 33, OR-NOT 30 OR 36 is outputted on lines 51,, 53 Signal G from element OR 33 through element OR 24, generator 27 goes to line 54j. Pulse 1 comes through line 54, element 3, line 54 to the counting input of counter 73 of block 4.

When sampling bus 51 according to the settings signals from bus 5 (at signals 1 552 52, 59 D 1 50j), the signal 1 from the output of element I 46 will set the trigger 40 to 1. Signal 1 on line 1.2 will turn on element 3i, and bus lines 5 and 5 / I connects The signal 1 from the trigger 40 through the elements AND 37, OR 31, OR-NOT 28, OR 34 is output on the line 51 ,, 50, 53:,. Signal 1 from the element OR 31 through the element OR 22, generator 25 will go to line 54. Pulse 1 will go through LI1-1IYU 54, element 3 ,, line 54 2 to the counting input of counter 73 of block 4.

When sampling a bus 5 j according to the tuning signals from bus 5 (at signals of 1 59 L 1 50,) signal. 1 from the output of the element AND 47 will set the trigger 41 to 1. Signal 1 on line 15 will turn on element 3, and the bus lines 5j are connected. The signal 1 from the trigger 41 through the elements AND 37, OR 33, OR-NOT 30, OR 36 appears on the line 51J, 50 ,, 53j. Signal 1 from the element OR 33 through the element OR 24, the generator 27 will go to the line 54з. Impulse 1 will go through line 54. element 3i to the counting input of the counter 73 of the block 4-2.

When sampling bus 5y according to the tuning signals from bus 5j (at signals 1 52, 60 50,), the signal 1 s of the code of the And 48 element will set the trigger 42 into 1. Signal 1

l

line 14 will turn on element 3}, and bus lines 5, and 5 are connected. Signal 1 from trigger 42 through elements AND 37, OR 31, OR-NOT 28, OR 34 IQ, 3, t, 45

70 25 hh ,,

444799

On line 51 ,, 50 ,, 53. Signal 1 from the element OR 31 through the element OR 22, the generator 25 will arrive on line 54. Impulse 1 will go through line 54, element 35, line 54.

on the counting input of the counter 73 block 4 ..

When sampling bus 52 according to the signals from the bus setting 5 h (at signals 1 56j 52j 60 / I 1 50,) signal 1 from the output of element I 49 sets the trigger 43 to 1. Signal 1 on line 16 will turn on element 3 2uI bus lines 5, and 5 is connected. Signal 1 from trigger 43 through elements AND 37, OR 32, OR-NOT 29, OR 35 is transmitted on line 51 ,, 50, 53. Signal 1 from element OR 32 through element OR 23, generator 26 goes to line 54. Impulse 1 will go through line 54. element 3, line 54 j to the counting input of the counter 73 of the block 4h. The work of the decoder 61 (Fig. 4) proc; - walks as follows.

Signal 1 on line 58 is Wits, if the inputs of the And 63 element receive signals:

1 62 L 1 17 L 1 66., ..

(ABOUT

Signal 1 on line 59 in Wits, if the input element And 64 enters

signals:

 G 62 l 1 17 l 1 66 50, l

 50 (2)

Signal 1 on line 60 is Wits, if signals are sent to the inputs of AND 65:

1 62 L 1 17 l O 50 ,, 50 A 50z A H 66 J. (3)

Otherwise, the signals O. will appear from lines 58-60.

The operation of block 4 (Fig. 6) is as follows.

According to the commands of the I / O controller that are similar in function to the I / O controller commands, data bytes sent to the PC 7 are recorded in the memory 70 of the block 4. Upon completion of the recording, the block 4 automatically switches to the programmed work mode with direct memory access - suspending the operation of its processor . At the same time, each byte of data transmitted over the line 50-52, 86, 57, 56, 55, 66 is intended to lay a channel step — to adjust the triggers 38-43 of the neighboring block 18. After finishing the channel setup, block 4 — the master provided There is an opportunity for data transfer with the channel modules to its initiator distributor. Further, the corresponding command resets the memory of block 4 - resetting the channel setting.

On command, the output signal of the A.000 and data byte 00000100 is output via lines 83 and 82 of bus 6 and lines 122-129 of 7, accompanied by signal 1 on line 81. If codes A coincide, the output of circuit 67 produces a signal 1 through line 87 to the inputs of the element I 68 and the decoder 72, and with this in mind signal 1 is inserted through line 91 to the synchronous inputs of the trigger 114-121, 1 is written to the trigger 119, the output of the one-vibrator 111 via the line 84 is reset those of block 4 (triggers 69, 108 ... 109, ..., 104, ..., 105, 114-121, counters 73, 74 are reset).

On the command Output Address A.001, the tuning byte, pulse 1 on line 81 is similar to that described for the command Output on the output of the decoder 72-, signal 1 on line 90 is sent to the clock inputs of the trigger 108 ... 109, and the Setup white is written to the register formed these triggers. Similarly, data transfer to other registers at their addresses 010-101 can be performed.

On the command Output address A.000, the control byte 1XXX1000, 1 on the line 81, as described in the triggers 114-121 of memory 70, the control byte will be written - 1 114, ..., ..., on line 53 to the processor Signal 1 will arrive and put it into suspend mode. The processor will reach 1 through line 78 and if there is 1 at the output of trigger 118, this will trigger the one-shot 110, from its output through line 94, pulse 1 will go to the inputs of the I-CLI 71 element circuit and trigger 69. Trigger 69 will be set to 1. Signals of XXX code - a program of a given number of tuning steps from the outputs of the 115-117 flip-flops along the lines 95 are fed to the inputs of the circuit 76, from its .. output signal O through the line 96 is fed to the inputs of the element I 68 and the trigger 114

From the output of the element I 68, the signal O is transmitted through line 80. Pulse 1 through line 94 through the element AND-OR 71 is sent to the counting input of counter 74, its contents will increase by 1, Code 001 from the outputs of counter 74 will go to the inputs of the decoder 75, signal 1 on line 93 it will arrive at the inputs of the elements And 106 ... 107, thereby the byte of the first step of the tuning will be read from the triggers 108 ... 109, through the elements OR 99 ... 100 ,. .101, keys 97 ... 98 along lines 50-52 to bus 10, along line 86 to the input of the element AND-OR 71, along lines 55-57, 66 to bus 6. If the tuning step is complete, then line 54 pulse 1 to the inputs of counter 73 and the element AND-OR 71, the contents of counter 73 is increased n 1. If 1 54 L 1 86, then from the output of the element AND-OR 71 pulse 1 will increase the contents of counter 74, the next tuning step will begin The channel of the read contents of the corresponding register 70 of memory of block 4. Each next step of setting up the channel is performed similarly. If 1 54 86, then the completed routing of the channel is maintained until it is reset. When the signal codes at the inputs of the circuit 7 coincide, it outputs signal 1 via line 96 to inputs of the I -68 element (its output on line 80 is signal 1) and trigger 114 (it is reset), and from its output, signal along line 53 About the input of the processor - the suspension is over.

The processor can use it to exchange data with other channel modules.

Upon completion of the described step on command Output, the memory 70 of unit 4 is reset and, therefore, the flip-flop circuits 38-43 are reset.

Claims (1)

Invention Formula A priority service switchboard system that contains a switching unit and a control unit, the switching control control output group of which is connected to the control unit 1 of the main inputs of the switching unit from the first to the third, the informational inputs-outputs of the switching unit are connected to: the first 7 on the third one, in order to broaden the scope of application by providing software settings when laying the commutation channels and decentralizing the priority service, it additionally contains three program channel setting blocks, each of which contains the element AND, the AND-OR element, two comparison circuits, two counters, two decoders, a trigger, and a control register memory node, and the commutation control block contains a priority dial, two groups of AND elements, a group of triggers, three OR-NOT elements, nine elements OR, three generators of single pulses, the first output of the priority decoder is connected to the first direct inputs of the first and second elements AND of the first group, the second output of the priority decoder is connected to the first and the first elements of the third and fourth elements I of the first group The third output of the priority decoder is connected to the first and fifth inputs of the fifth and sixth elements of the first group, the outputs from the first to the sixth elements of the first group are connected to the installation inputs of 1, respectively, from the first to the sixth group triggers, the output of the first group trigger is connected to the first input of the first an element of the second group, the first one is the string, ,,; - channel, the inverse inputs of the second and the biometric input of the decoder of the priority four elements of the first group are connected to the first input of the eighth OR element and connected to the volume and the first output of the switching control of the switching control unit, output control switching group which is connected to the second strobe 1m input of the priority decoder, to the output of the second trigger group and the first input of the second element And the second group, the output of which is connected to the first inputs ne first- and second-OR element and the first OR-NO element, a third output latch group connected to the first input of the third AND gate the second via the assembly OR outputs - 4Q of the second common bus node of the control register memory of the first to the third blocks of the program channel tuning, the inverse inputs of the third and fifth elements AND 4g of the first group are connected to the first input of the ninth element OR and connected to connected via the assembly OR outputs of the occupation sign of the third common bus of the control nodes the group with the third gating input gQ of the register memory from the first priority priority trader and the third output of the switching control of the group of the switching control unit, the fourth output of the switching control of the group of which is connected to the fourth gate input of the priority decoder, with the output of the fourth trigger and the first input of the fourth element And the second group, the output of which 55 the program channel settings block, the output of the first element OR is connected to the second input of the eighth element OR, and is connected to the output of the occupation sign of the second common bus of the system switch, the output of the third element OR is connected to the second input of the seventh element OR, and is connected to the output of the occupation sign of the first 1444799 connected to the second inputs of the first and second elements OR and the first element OR NOT; the output of the group's fifth trigger is connected to the fifth gate input of the priority decoder, to the first input of the fifth element AND of the second group and to the fifth output of the control switching of the group block switching control, the sixth output of the switching control of the group of which is connected to the sixth gate input of the priority decoder, to the output of the sixth trigger of the group and to the first input of the second element AND of the second group, the output of which is connected to the first inputs s of the third and fourth elements OR and the second element, the second inputs of which are connected to the output of the first element AND of the second group, the output of the third element AND of the second group are connected to the first inputs of the fifth and sixth elements OR and the third element OR NOT, the second inputs of which are connected to the output of the fifth element And the second group, the inverse inputs of the first and sixth elements And the first group are connected to the first input of the seventh element OR and are connected to the integrated one through the mounting G1I outputs of the occupation sign of the first common bus node From control register memory from the first to the third program setting blocks via the assembly OR outputs — the sign of the second common bus of the control register memory nodes from the first to the third blocks of the channel program settings; the inverse inputs of the third and fifth elements of AND of the first group are connected to the first input of the ninth element OR and are connected to the combined through mounting OR to the outputs of the occupation sign of the third common bus of the control nodes five the program channel settings block, the output of the first element OR is connected to the second input of the eighth element OR, and is connected to the output of the occupation sign of the second common bus of the system switch, the output of the third element OR is connected to the second input of the seventh element OR, and is connected to the output of the occupation sign of the first 91 shared bus system switch the output of the fifth element OR is connected to the second input of the ninth element OR and connected to the output of the sign of the third common bus of the system switch, the output of the seventh element OR is connected to the input of the first single pulse generator, the output of which is connected to the counting input of the first counter and the first input of the element AND-OR of the first block by software channel settings, the output of the eighth element OR is connected to the input of the second generator of single pulses, the output of which is connected to the counting input of the first counter and the first input To the element of the second programmable channel setting block AND-OR, the output of the nine element OR is connected to the input of the third generator of single pulses, the output of which is connected to the counting input of the first counter and the first input of the And-OR element of the third programmable channel setting block, the outputs of the second, fourth and the sixth OR elements are connected respectively to the outputs of the sign of the first slave module, the sign of the second slave module p and the sign of the third slave module of the system switch, the output of the first element OR is NOT combined through the installation OR with the first interrupt input of the system switch and connected to the first information input of the priority decoder, with the second inputs of the fifth and sixth elements AND the second group and the installation inputs into the OL and sixth group triggers, the output of the second element OR is NOT combined through the mounting OR with the second interrupt input of the system switch and connected to the second information input of the priority decoder, the second inputs of the third and fourth elements of the second group and the installation inputs of the third and fourth In addition to the group triggers, the output of the third element OR is NOT connected through the mounting OR to the third interrupt input of the system switch and connected to the third information input of the priority decoder, to the second inputs of the first and second elements of the second group and the installation inputs O of the first and second triggers of the group, the second direct inputs from the first to the sixth elements And the first group are connected to the integrated through the installation 799 new 5 0 5 5 ten OR to the codes of the choice of the bus of the nodes of the control register memory from the first to the third program channel setting blocks, the outputs of the code for controlling the interruption of the nodes of the control register memory from the first to the third blocks of the program setting are combined through the installation OR or connected respectively to the fourth to the sixth information inputs priority decoder, the synchronous input of the system switch is connected to the seventh gate of the priority decoder, the reset input of the system switch is connected to the reset inputs the first and second counters, triggers and the first inputs of resetting the control register memory nodes from the first to third channel program setting blocks, the outputs of the first and second k-th counters (to 1.3) of the channel program setting block are connected respectively to the first input of the comparison circuit and the input of the first decryption to the program setting block of the channel, the output of which is connected to the input of the read address of the node of the control register memory of the program setting block of the channel, the output of the code of the steps of the setting of the control node the register register of the k-th channel program setting block is connected to the second input of the first 5 comparison circuit of the k-channel program setting block, the output of which is connected to the second reset input of the control register memory node and the first direct input of the Ik-k element unit for program channel tuning, the second direct input of which is connected to the gate input of the second decoder and the output of the second circuit of the comparison kth program channel tuning unit, the first and second inputs of which are connected respectively to the input code the address of the k-th block of the program setting of the system switch channel and to the address field of the k-th common bus of the system switch, the second input of the AND-OR element is connected to the installation input at the O flip-flop and the output of the output of the control register node of the k-th block of the program channel settings, resolution input: output, record address input, information input, output of the sign of the tuning mode, sync input and output of the bus capture flag 0 0 0 55 111444 connected respectively to the trigger output, the output of the second decoder of the k-th channel program setting block, the data field output of the k-th common bus of the system switch, the third input of the AND-OR element of the program-channel setting block, the output and the capture sign k th common bus system switch, y output of the element AND-OR and the information input of the second decoder of the k-th block 99I iiporpaMMiioti channel settings are connected respectively to the counting input of the second counter of the k-th program setting block of the channel and the address of the address field (.: data of the k-th output 1S1 of the system switch, input and output of the input of the k-o o6mevt bus of the system switch are connected respectively to the output and inverse of the input element AND of the k-th block of program channel settings. 1 ff / 5 f f E5 and "Zo o cvS S 5 f2l FIG. eight