SU1439622A1 - Device for monitoring electric connections - Google Patents

Abstract

The invention relates to circumlati Automation, computing and electrical measuring equipment and can be used to control the electrical connections of the installation of devices. blocks, harnesses and cable joints. The aim of the invention is to reduce the hardware costs, Imago allows you to control all types of wiring connections, to determine the number of the conductor in the cable and the numbers of all the closed conductors without each other. The goal is achieved by the fact that a device containing a clock pulse, an address counter, a switch, three pulse shapers, an output unit, a comparison circuit, a interface block with the control object, a channel number register, a mode setting block, two nodes of the first pulse, series counter and channel number counter. 6 Il. S (l

Description

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The invention relates to the field of automation, computing and electrical measuring equipment and can be used to control electrical connections for mounting devices, blocks, wiring harnesses and cable connections.

The aim of the invention is to reduce the hardware cost of the device.

FIG. 1 is a block diagram of the device; in fig. 2 through 6 are functional diagrams of the interface block with the control object, the second and third impuls formers, and the first and second extraction angles of the first pulse.

The device contains (Fig. 1) a clock pulse generator 1, an address counter 2, a switch 3 connected to the object 4 of the counter; , 5 series counter, first pulse shaper 6, interface 7 with the test object, channel number counter 8, second and third drivers 9 and U.impulses, channel number 11 register 11, mode setting block 12, first and second nodes 13 and 14 in the gap of the first pulse,

After the power is turned on, shaper 6 generates a Pause signal, which disables the operation of switch 3 and rewrites the contents of counter 2 addresses into a 5-series counter. After the termination of the Pause signal, the switch-3 operation is allowed, the address inputs from the outputs of counter 2 are supplied to its address inputs, and the information input receives pulses from the generator 1. At the same time, these pulses go to the subtracting input of the counter 5. The zero signal - counter 5 increases by one the contents of counter 2, initiates the generation of a signal from the Pause generator 6. The Pause signal prohibits the injection of clock pulses to the input of the switch 3 and loads into the counter 5 the following reference value 15 and the output block T6.

The Safeguard Unit with the address control object. Thus, the transmit- tor contains (Fig. 2) the probe 17 and the amplifier.

each channel has a series of pulses,; moreover, the number of pulses in a series is equal to the numerical value of the channel number, and the series of adjacent channels are separated in time by the duration of the Pause signal. After iterating through all the channels of the switch 3, the process is repeated from the starting address, which is arbitrarily set by the counter 5 to turn on the power.

From the outputs of the switch 3 series im35

18. The formers 9 and 10 (Figs. 3 and 4) contain one-shot 19 and a reference element 20. Nodes 13 and 14 (figs. 5 and 6) consist of AND-NE elements 21,

The address counter 2 is for 41Orming the current address.

Switch 3 is designed to feed the channel with the current address number of the normalized pulse train. Q A 5 series counter is designed to form a normalized pulse train. Block

7 mate with object of contact

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a channel measure, and node 14, to form a reset signal for node 13.

The comparison circuit 1b is intended to compare the fixed and the current channel number codes. The output unit 16 is for outputting control results.

YcTpoficTBo works as follows.

After the power is turned on, shaper 6 generates a Pause signal, which disables the operation of switch 3 and rewrites the contents of counter 2 addresses into a 5-series counter. After the termination of the Pause signal, the switch-3 operation is allowed, the address inputs from the outputs of counter 2 are fed to its address inputs, and the information input receives pulses from generator 1. At the same time, these pulses go to the subtract input of counter 5. The zero-signal of counter 5 increases the content by one counter 2, initiates the generation of a signal from the Pause generator 6. The Pause signal prevents the clock pulses from entering the switch 3 and loads the next pulses into the counter 5 to the inputs of the control object 4. In case of a closure between

The role is designed to remove the normalized D5 channels at the test object on each series of the test channel of the test object, matching signal levels. The channel number counter 8 is for counting the number of pulses in normalized runs. The channel number register 11 is intended to fix the channel number code.

Block 12 is designed to input the Reset and Step signals that control the operation of the device, and can be implemented in the form of two buttons, for example, a control panel.

Node 13 is pre-pumped to form a write signal to register 11 but 0

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a house of closed channels contains a series of pulses belonging to all closed channels due to the Mounting OR operation between the corresponding outputs of the switch 3 and the separation of the series of pulses over time.

Using block 7, the input of the receiving part of the device is connected in series with the outputs of the control object 4 and the matching of the signal levels from the control object outputs and the signal levels to the input of the receiving part of the device is carried out. The receiving part of the device is connected with the transmitting part only through the control object.

Suppose that in the control object the channels n, m and k are closed, and the channels n and ha are adjacent. After connecting the receiving part of the device to the channel under test, for example, it is necessary to reset the receiving part of the device by resetting the signal. On this signal, the channel number register 11 is nullified, node 13 is reset, and node 14 is cocked. On the leading edge of the first pulse of any first series (n, ha or k), driver 9 removes the reset signal of counter 8. At the end of the series, after a time equal to the delay time on the driver 10, a gate signal of the comparison circuit 15 is generated at its output, since the register 11 is reset, then the second inputs of the comparison circuit 15 are given a zero code, and the first inputs are supplied with a code of the number of pulses in the series from the counter 8, the output of the comparison circuit 15 signal Comparison is not odds is measured, and the Incomparative signal is generated at the inverse output. Node 13 transmits a signal. A noncomparison at the input of the record of register 11. Register 11 records a code of the number of pulses in this series and feeds it to block 16. Assume that the series of the channel is n. At the end of the series, after a time equal to the delay time on the driver 9 , at its output a reset signal is generated for counter 8. The delay time of driver 9 is longer than the delay time of driver 10. When other series (t and k) arrive, counter 8 will read the number of pulses in the series, the comparison circuit 15 will generate an Incomparison signal, but the recording signalRegister 11 will not be formed, because the release assembly 13 is not reset. Node 14 all this time is in the cocked state and does not respond to the signals. Comparison

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the time of passage of the series, the code of which is fixed in register 11. When a signal arrives, Step 14, the node 14 is reset and is in this state until the signal arrives Comparison, i.e. before the arrival of the series recorded in register 11. On the signal of comparison, node 14 is cocked and generates a signal that resets

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node 13. Upon receipt of a series following this one (since the code of the series is fixed, the next series is), the comparison circuit 15 generates a signal of Incomparability which passes through node 13 to the input of the record of channel number 11.

Thus, in the register 11 the code of the number of pulses is recorded with the arrival of the signal Step. In register 11, channel numbers will be fixed and issued to output unit 16 codes of all subsequent series. When receiving the code previously recorded in register 11, the step signal should be stopped, since all the closed channel numbers are already fixed, and proceed to check the next channel.

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Claims (1)

Formula of the invention nor A device for controlling electrical connections, containing an address counter, connected by an output to an address input of a switch, whose outputs are outputs of a device for connecting to the inputs of a control object, and a switch control input connected to the output of the first pulse shaper, clock generator, interface block with the control object, the inputs of which are the device inputs for connecting to the inputs of the control object, the channel number register, the output connected to the output of the output unit, the task block The press, the comparison circuit and the second and third pulse shapers, which are different from the fact that, in order to reduce the hardware costs of the device, a series counter, a channel number counter, and two nodes of the first nm-Pc are inserted, the output of the clock generator is connected to the information input of the switch and the subtracting input of the series counter, the information input and recording entry of which are connected respectively to the output of the address counter and the first pulse generator, and the output to the counting input of the address counter and input The first pulse shaper, the output of the interface unit with the object is connected to the trigger inputs (the SECOND and third pulse shaper and the counting input of the channel number counter, the output connected to the information input of the channel number register and the first information input of the circuit are compared: and, the second information input which is connected to the output of the register of the channel number, and the inverse and direct B1 and 1 inputs, respectively, with the information 1; the first inputs of the first and second nodes of the first pulse, the reset inputs of which By connecting to first and second outputs of the block zada10 to the input of the recording of the register and the input of the permission of the first selection and the output of the task block with the input of the reset of the regula and the input of the allocation of the first and the input of the circuit, the output of the third pulse, which is connected to the first pulse generator 4 t.f tj J 14 J chl. Il, XJUi vv Lt.i j v tJJVJivtA- j, .i. V%, (- i, .r v "j NIA mode, a outputs - respectively 15 chick channel numbers. to the input of the recording of the channel number register and the resolution input of the first selection node of the first pulse, the first output of the mode setting unit is connected to the reset input of the channel number register and the resolution input of the second selection node of the first pulse, the gate input of the comparison circuit is connected to the output of the third pulse generator allowing the input is connected to the first output of the second pulse shaper, the second output of which is connected to the reset input count i. V%, (- i, .r v "j 9ig.2 Phase 3 9gL 9ag.5 ig.6