SU1439589A1 - Data analysis device - Google Patents

Abstract

The invention relates to computing and can be used in systems for the automated processing of large volumes of information, for example, for solving the problems of planning and managing the branched multi-product production cooperatives of enterprises, where high demands are placed on the reliability of information. The purpose of the invention is to increase the reliability of data analysis. The device for data analysis contains a block of 5 control groups of data, groups of elements 6 and 10, a register 9 of groups of data, a block of control 7, a generator of 8 clock pulses, a block 11 of monitoring sequences of groups of data, a block 12 of data output. 1 hp f-ly, 1 tab. 4 il. with S (L

Description

U

four

00 (o

sd

eo: o

 The statement is related to computing and can be used in automated systems for processing large volumes of information, for example, to solve problems of planning and defining branched multi-purpose production enterprises that have high reliability requirements for information.

The purpose of the invention is to increase the reliability of data analysis.

On fi1. 1 shows a block diagram of a data analysis device; FIG. 2 is a block diagram of a control unit of data groups; Fig. 3 is a block diagram of a control block of the sequences of data groups of Fig. 4 a block diagram of a control block;

The device (FIG. 1) contains a block of input, data, block 2 of input reference dependencies 5 block 3 of the input memory

five

0

Information on the relevant parameters of the controlled system is fed to the input of data input unit 1. Block 1 are input devices from punched cards (punched tapes), devices for receiving information via communication channels, etc. The pre-formed reference (reference) dependencies between the data types that the input data must satisfy are entered as logical expressions or analytical dependencies through the input of the reference dependency input block 2 and stored in memory 4 of the reference dependencies in tabular form.

Unit 2 can serve as the screen of the video terminal, computer typewriter, and so on.

 Blocks 3 and 4 of the input data and reference dependencies are the DZU.

The control is carried out in the process of multistep two-step analysis.

danss, block 4 of memory of reference memory-25 for data.

bones; block 5. control data groups, the first group of elements And 6, block 7 control., generator 8 clock pulses. registrar 9 groups of data, the second group of elements AND 10 block 11 of control sequences of groups of data groups block 12 of data output, containing block 12.1 of memory of single data block 13 of clocks.

The control unit of the data groups, shown in FIG. 2, contains the first group of E elements And 14, the first and second shift registers 15 and 16, register 17, the first comparison circuit 18, the encoder 19 the second comparison circuit 20, the second group of elements 21, trigger 22

The unit 5 for controlling the sequences of data groups (FIG. 3) contains the first register 23, the third group of elements AND 245 the second register 25, mode 2.6 comparisons, the second group of elements 27, the node 28, the decryption j trigger 29, the element 30, the first a group of elements And 31, a store memory 32, consisting of n1 of n successively connected two-way communications of the shift registers 33,

The control unit 7 (FIG. 4) contains the first, third, fourth, second elements AND 34-37, the second, first, third elements HE 38-40 and. ILI41.

The device works as follows.

0

five

0

First stage. Local control of the data group.

In block 5, the control of data groups in the on state is sequentially read from block 3 of the input data memory information and checked for compliance with the reference dependencies from block 4 of the memory of the reference dependencies. If the result is positive, the data checked through the And 6 elements are rewritten into the data group memory block 9, when an error is detected, the entry into it is blocked, and the control block 7 responds to an error signal and the operation is stopped; In the absence of errors, in block 9 of the data group accumulate data having the same values of the identifying attribute of the group. When changing from this sign (transition to another group), control unit 9 turns off data group control unit 5 and turns on data group sequence control unit 11.

Second phase. Global control of data group sequences

In block 11, the control of the groups of data in the on state is read the information accumulated in block 9 of the memory of the groups of information and checks its consistency with the history recorded in block 11 of the control of the sequences of groups of data. If the test is positive, the data through the elements 10 is recorded in the output data storage unit 12, and the control unit 7 turns off the data group sequence control unit 11 and turns on the data group control unit 5. When an error is detected, the recording in the output data storage unit 12 is blocked, the control unit 7 executes the signal 1Q. The contents of register 25 are fed to

error is terminated and work is stopped. If there are no errors in the output memory block 12, all groups of data are accumulated. They are output for further processing. The control unit 7 performs the sequential activation of the data group control unit 5 and blocks the output of data in the presence of errors.

Unit 5 of the control of data groups works as 2Q.

the first input of the comparison circuit 26, to the second input of which, through the elements 31, are fed sequences of data groups from the shift registers 33 of the 15 gaseous memory 32 (history) until a box is received; itel: the first result of the comparison, fixed: in register 29 and stopping, through the item NOT 30, the store memory reading. In the case of a positive result, comparing the And 2 elements into the store memory of the contents of the register 23, an error signal appears at the output of the block when the result is negative.

In each clock cycle specified by the generator 8, a clock pulse is sent to the first input of the block, allowing writing to the shift register 15 data 25 sent to the second input of the block. At the same time overwriting the data previously contained in the shift register 15. The shift register 16 causes this.

15

That in these registers there are always T current and previous data. The results of comparison, by scheme 18, of the comparison of signs identifying that these data belong to the same group.

ne ,, is fed to the second output of the block and allows the flow to the comparison circuit 20 of the reference dependencies between the data types arriving at the third input of the block. The combination of current and previous data, formed in register 17, after being classified in encoder 19, comes in the form of a combination of data types in a circuit .20 Comparison with the underlying dependencies between data types. The encoder 19 classifies the input data, i.e. converts specific data values into data types, and is implemented in B1 beyond the traditional combinatorial scheme on AND, OR, NOT elements. The truth data of the encoder 19 is shown in the table. The result of the comparison is recorded in the trigger 22 and is fed to the first output of the block as an error signal (or no error signal).

Unit 11 of the control sequence of data groups works as follows. In each cycle, set by 1 generator 8, to the first input of the block

a clock pulse arrives, allowing / holding a record through the decryption node 28 to registers 23 and 25 of the group of data supplied to the second input of the block. Node 28 produces a breakdown of data groups into two data sets and is implemented as a typical combinatorial scheme on elements AND, IL, NOT (FIG. 3),

the first input of the comparison circuit 26, to the second input of which, through the elements 31, sequences of data groups from the shift registers 33 of the gas memory 32 (history) are fed until a box is received; itel: the first result of the comparison, fixed - rueG: in the register 29 and stopping through the NOT 30 element the store memory reading. If the result is positive, comparing through the elements of AND 2, the contents of the register 23 are written to the store memory, with a negative result, an error signal appears at the output of the block.

The encoder classifies the data, B (:; there are six components

nent

,, d

05

Q beef

five

0

five

O

five

into three classes: K - ito-K ,, - averaged data, K 3 - simple (elementary) data. For each class, reference dependencies are selected that determine the admissibility of following the data in the group. The remaining combinations of the data components are prohibited and are not included in the table.

The control unit 7 alternately turns on and blocks the first output of the data group control unit 5, the second output controls the data group sequence control block 11, and also blocks the third output to issue data for further processing when an error is detected, depending on the signals at the first, the second, third Ji fourth entrances. The control unit implements the following logic functions:

OUTPUT U INPUT 2 INPUT 3 & INPUT 4;

 OUTPUT U INPUT 2 & INPUT 3 &

INPUT 4;

OUTPUT IV INPUT 4, where INPUT 1 - no error at

control group dan.ngh; INPUT 2 - transition to another group

data; INPUT 3 - clock pulse;

five

INPUT 4 no error while controlling the data sequence.

The operation of the device is synchronized with the clock pulses generated by the generator 8 and supplied to the circuit elements according to FIGS. 1 - 3.

The device can be used to control formalized informational messagesJ describing schemes for the delivery of various enterprises to complete sets of products going to the production of intermediate-day (complete) and final products. : Such schemes may include thousands

A large number of onshops are allowed, leading to the reliability of subsequent calculations, which are given; to the need for an effective system of control of input information "

Claims (1)

1. A device for data analysis, containing a data group monitoring unit, a pulse generator, a control unit, a data output unit, the output of the clock pulse generator connected to the clock inputs of the control unit and the data group control unit, the output of the data output unit The information in the device code, the data input and the input of the reference dependencies of the device are connected respectively to the first and second information inputs of the data group control unit, about t and h and rain; e with so 5 that, in order to increase reliability, data analysis, the device is co, o; it has two groups of elements AND, a register of data groups and a block of sequences of data groups, the first and second and third outputs of the control unit are connected respectively to the block enable input control of data groups, the enable input of the control unit of the sequences of data groups and the enable input of the data output unit, the error output of the control unit of the data groups c50 of the control unit of the data groups, the second information input of which is connected to The information inputs of the elements of the second group, the output of the encoder is connected to the first information input connected to the first permitting input of the control unit and gating inputs 55 D ° of the second comparison circuit, the second input element of the AND group of the first group whose information input is connected to the outputs elements of the second group, to the data input of the device, the output to the output of the second comparison circuit is connected to the sign of the identification of the group of the block with the information input of the trigger 0 the data groups are connected to the second permitting input of the control unit, the outputs of the elements And the first group are connected to the information input of the data group register, the synchronization input of which is connected to the output of the clock pulse generator, the outputs of the data group register are connected to the information inputs of the data group monitoring unit. elements of the second group, gating those inputs and the third permitting; iy input control unit 5 is connected to the error output of the control unit of the sequences of data groups, the clock input of which is connected to the output of the clock pulse generator., The outputs of the elements And the second 0 groups of connections are yucheny to the information input of the data output unit, moreover, the control unit of data groups contains one group of elements I, two shift registers, two comparison circuits, a trigger, 5 register and encoder, information input; which is connected to the output of the register, the synchronization input of which, the synchronization inputs of the first and second shift registers and the trigger are connected to the clock input of the control unit of the group, the data whose resolution input is connected to the gate inputs of the elements of the first group, whose information inputs form -jg the first information input of the data group control unit, the outputs of the elements AND of the first group are connected to the information input of the first shift register, the output of which is connected to the information input of the second shift register and with the first information inputs of the first comparison and register, the output of the second the shift register is connected to the second information The 45 inputs of the first comparison circuit and register, the output of the first comparison circuit is connected to the gate inputs of the AND elements of the second group and is the output of the identification tag .groups 50 of the data group control unit, the second information input of which is connected to the information inputs of the elements of the second group, the output of the encoder is connected to the first information input 55 ° C of the second comparison circuit, the second information input of which is connected to the outputs of the elements of the second group, the output of the second comparison circuit is connected to trigger information entry, you71 the course of which is the output of the error of the data group control block, the control block of the sequences of data groups contains three groups of elements AND, two registers, a trigger, a comparison circuit, a store memory, a decryption node and a NOT element, whose code is connected to the first inputs of the AND elements the first group, the second inputs of which and gating inputs of the elements of the second group are connected to the resolution input of the control unit of the sequences of data groups, whose information input is connected to the information inputs of the elements second and second the second group, the outputs of the elements of the second group are connected to the input of the decryption node, the first and second outputs of which are connected to the information inputs of the first and second registers, respectively, whose synchronization inputs and trigger synchronization input are connected to the clock input of the group of sequences of data groups, the output group store memory is connected to the third inputs of the elements AND of the first group, the outputs of which are connected to the first information input of the comparison circuit, the second information input of which is connected to the output the second register, the output of the comparison circuit is connected to the information input of the trigger, the output of which is connected to the input of the element 35 NOT, gating inputs of the elements And eye exits block. 1 1 1 one about 1 1 1 1 1 1 о о о 1 1 о о eight The third group is the error output of the control unit of the sequences of data groups, the output of the first register is connected to the information inputs of the AND elements of the third group, the outputs of the elements AND of which are connected to the information input of the store memory. 2, the device according to claim 1, characterized in that the control unit It contains four elements AND, an element OR, and three elements NOT, the first permitting input of the block is connected to the first inputs of the first and second elements AND, and through the first element NOT to the first input of the SH, the second permitting input of the block is connected to the second input of the second AND element and through the second element NOT to the second input of the first element AND, the third permitting input of the block is connected to the third inputs of the first and second elements AND, and through the third element NOT to the second input of the OR element, the output of which is the third code of the block, The clock input of the block is connected to the first inputs of the third and fourth elements, And the second input of the third element And is connected to the first element And, the second input of the fourth element And is connected to. the output of the second element AND, the outputs of the third and fourth elements AND are respectively the first and second outputs of the block. Ltd one oh oh oh oh about about 1 about 1 about o 1 1 eleven about about about 1 1 oh oh