SU1432559A1 - System for controlling process complexes - Google Patents

Abstract

The invention relates to automatic control and can be used in the construction of distributed control systems of technological complexes. The purpose of the invention is to increase the capacity of communication lines by reducing the transmission waiting time for each local control unit. The control system of technological complexes contains N local control devices, a communication line, N communication devices with an object, and an initial device for the exchange of priorities. The local control device through the communication device with the object controls the technological object, displays the information received, interacts with similar control devices. The exchange of information between individual local control devices is carried out in accordance with a system of dynamic priorities. The current value of the priority of information depends on the expectation of transmission, the initial priority of information and the priority of this local control device. The link access is obtained by the local control device with the highest priority information at a given time. The initial exchange device is the initiator of the beginning of the exchange between local control devices. The invention provides a high flexibility of information exchange in the system and an increase in the efficiency of using communication channel facilities. 3 hp f-ly, 5 ill., 1 tab. to (L 4 SO I ate with

Description

The invention relates to automatic control and can be used in the construction of distributed control systems of technological complexes.

The aim of the invention is to increase the capacity of communication lines by reducing the transmission waiting time for each local control device.

Pa figs. 1 is a structural diagram of an industrial control system; FIG. 2 is a block diagram of a local device; in fig. 3 - 5 message formats; Fig. 4 is a block diagram of the control unit; in fig. 5 is a block diagram of the device of the initial exchange of priority.

The control system contains local control devices, communication line 2, devices 3 -, - 3 communications with the object and device 4 for initial exchange of priorities.

The local device 1 controlled 25 contains (FIG. 2) the central processor 5, the memory block 6, the input / output unit 7, the interface block 8, the system bus 9, the control block 10, the decoder 11, the second memory block 12 - - JQ TI, first counter 13 pulses, encoder 14, switch 15, second counter 16 pulses, third memory block 17, first converter 18 codes, D-flip-flop 19, element 20, transceiver 21, second converter 22 codes and inputs- outputs 23-34 device blocks.

The control unit (Fig. 4) contains the first one-shot 35, the first 36 and. the second 37 nodes are the comparison decoder 38, the first element is And 39, the first D is the trigger 40, the second element is And 41, the second one-shot 42, the inverter 43, the third element 44, the first timer 45, -.c the first RS flip-flop 46, the first element OR 47, the counter 48 pulses, the second timer 49, the second element OR 50, the second RS-flip-flop 51 and the node 52 of the initial installation.

The initial device for the exchange of priorities contains the element 53 launch (integrated RC-chain), the element is NOT 54, the shift register 55, the first 56 and the second 57 blocks of permanent memory, the first element OR 58, the first element And 59, the second element And 60, the second element OR 61, the converter 62 codes and the transmitter 63.

35

50

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The proposed system dynamically prioritizes the information transmitted by each local control device, Tekup, its priority value depends on the transmission waiting time, initial data priority and the priority of this local control unit. The link access is obtained by the local control device with the highest priority of the informant at the moment. Compared with the known systems, there is a higher exchange flexibility. form and increase the efficiency of use of the communication channel.

The control system (Fig. 1) is a complex of local control devices (i 1, N) that control one or several technological objects, process and display technological information. The interaction between the individual control devices 1, being connected via link 2, At any time, only one source device can transfer data blocks received by all other devices 1, -. However, the processing of the received information is carried out only by the device to which it is addressed. FIG. The format of the transmitted message containing a service block, n data blocks and an end block is given. The message service unit contains information about the address of the source device, the type of message, and the address of the receiving device.

Correctly received information is acknowledged by the receiving device by transmitting an acknowledgment (Fig. 36). If the source device did not receive a confirmation within the set time period, the message transmission is repeated. The data prepared for transmission by the local control devices 1 is assigned a certain priority value, depending on the priority of the given control device Q, the transmission waiting time, the initial priority of the data.

The source device is determined from the results of the priority exchange cycle as the device having the highest priority at a given time.

tet dan} 1st. The next priority exchange of the priorities starts after the transfer is acknowledged by the receiving device, or after a fixed period of time (Gz) after the end of its exchange cycle, if the confirmation is not transmitted. During the exchange of priorities, each device 1, the control, is allocated a period of time (t) when it can transmit messages with the current priority value of the prepared data (the message format is shown in Fig. Sound). Each device during the communication exchange compares its own priority with the priority of other devices 1-j, and if its priority is most I: tim, then this device 1 can start data transfer at the end of the exchange cycle. Devices 1 that do not receive the right to transmit increase the value of priority. The current data priority is selected from the set of valid priority values set for each device 1j-. The lack of data prepared for the data transfer corresponds to a zero priority, for all devices. In order to eliminate conflict situations, the sets of permissible values of priorities of different devices 1i should not have common elements.

Thus, in the system, three types of communication are possible; Data, Confirmation, Priority. The first message block is service and carries information about the type of the message, the spread of the source device, the receiving device, the priority, the last 1 ending block, common to all types of messages.

Local device 1 | control through the device 3j-communication with the object controls the technological object, processing and displaying the information received, the interaction with similar control devices If If (Fig. 2).

The central processor 5 is designed to perform operations in accordance with the program stored in. block 6 of memory. Unit 6 is intended for storing instructions, constants and intermediate data. As the central processor 5 and the memory block 6, for example, can be used.

from Q 5 0 5 about Q

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the corresponding modules, input p and e are part of the microcomputer Electronics 60.

The I / O unit 7 (peripheral equipment) provides the ability to monitor and quickly influence the object of control, store large arrays of information, display the state of an object, etc. It may include, for example, a floppy disk drive, display, EPM, and others. with the corresponding interfacing schemes, ensuring their joint work with the microcomputer Electronics 60.

The system bus 9 is a collection of lines that allow information to pass between the individual devices connected to it.

The interface unit 8 provides the central processor ry 5 with the ability to exchange information with the second 12 and third 17 memory blocks and the first counter of 13 pulses. In addition, the interface unit 8 provides the central processor 5 with the input of two discrete signals at the first and second inputs in the program exchange or interrupt mode.

The control unit 10 controls the exchange of information with other local devices 1; management

The depmfrater 11 generates an output level at the output when the input of the end message block arrives at erg. It can be implemented on the IC K155LLZ.

The second memory unit 12 is designed to store the received message and the service unit of the received message in the control unit 10. The received message can be read by the CPU 5.

After receiving the entire message, its service block is output at the output of memory block 12.

The first pulse counter 13 is intended to store the number corresponding to the current priority value of the local control device 1t.

The switch 15 provides for the passage to the first input of the second counter 16 pulses of the code from the output of the first counter of 13 pulses in the presence of an enabling level at the corresponding input (switch 15 and from the first

the output of the encoder 14 in the presence of a resolution level at the input of the switch 15.

The third memory block 17 is intended for storing data prepared for transmission and forming messages in accordance with the formats (Fig. 3).

The encoder 14 signals the outputs of the control unit 10 controls the operation of the switch 15 and the second counter of 16 pulses according to the table.

write the edits to the low bit of the shift register 55. The level of the logical unit from the first output of the register 55 through the OR element 58 enters the second input of the converter 62 codes and allows the converter 62 to pass the code from the output of the block 56 of the permanent memory. The contents of the block 56 of the permanent memory is the code corresponding to the format of the service unit (Fig. 36). Service block from the first output of the converter 62 through the transmitter 63 to the post

20

A converter of 18 codes provides 15 to the communication line. Having finished, it transmits the conversion of the parallel code, arriving at the first input, to the serial for transmission to the communication line, noise-resistant coding of information and the formation of the clock signal preceding each transmitted message block.

The second code converter 22 decodes the next message block and, in parallel code, decodes it to the input of the second memory block 12.

25

In this case, converter 62 sets the level of a logical unit at the second output. In this case, a high level appears at the second output of register 55, and a low level at the first. The input to the converter 62 receives a code from the output of the fixed memory block 57, corresponding to the format of the ending block. The code converter 62 and transmitter 63 are similar to converter 18 and transceiver 21, respectively.

Consider the operation of the system on the example of the functioning of a local

The transceiver 21 provides

The work of the system is considered as the functioning of the lock

conversion of information for transmission of control device 1;

When the voltage is turned on, a pulse from the output of the node 52 of the installation translates the RS-three unit state. When the triggers are reset, the counter 48 is reset. In addition to the dump processor 5, the reset signal sets the second 12 and third memory to reset and resets the device to this state until the first message of the type is generated. This message generates and In line 2 is a device exchange link. The reception at the output of the decoder ry translates the RS-flip-flop 4 state indicates the reception of this data. The log level from the inverse output Ger 51 permits the operation of T 45. This is the beginning of the priority sharing panel. According to the first level, the first time indicates the moment of time, the device 1 / manages to transmit a message with a priority message prepared

35

40

line / link, as well as reception and conversion of signals from link 2. The specific implementation of transceiver 21 depends on the type of link used, the range required and the reliability of the transmission, etc.

Line 2 provides signals between individual control devices 1. A light guide, coaxial cable, a pair of wires, etc. can be used as a communication line.

The devices 3 communicating with the object provide for the exchange of analog and 1-SHFROVY information with the control object according to the commands of the local control device 1 t. As devices 3, links with the object can be used functional blocks of the systems i ASBT-M, SMEVM, CAMAC, etc. The device 4 of the initial priority exchange is the initiator of the first cycle of the exchange of priorities. After the supply voltage is applied, device 4 transmits a message in accordance with the format (Fig. 36). When the supply voltage is turned on, the pulse from the output of the HE 54 element produces

45

55

goes on line. Having finished

In this case, converter 62 sets the level of a logical unit at the second output. In this case, a high level appears at the second output of register 55, and a low level at the first. The input to the converter 62 receives a code from the output of the fixed memory block 57, corresponding to the format of the ending block. The code converter 62 and transmitter 63 are similar to converter 18 and transceiver 21, respectively.

Consider the operation of the system on the example of the functioning of a local

o device 1 control;

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When the supply voltage is turned on, a pulse from the output of node 52 of the initial setup translates the RS flip-flop 51 into one state. In this case, the flip-flops 46 and 40 are installed and the counter 48 is reset. In addition, the central processor 5 signals the reset line to reset the second 12 and third 17 memory blocks and resets the counter 13. In this state, the device 1j until the first message of the type Acknowledgment is received. This message is generated and transmitted to the communication link 2 by the initial exchange device 4. The reception of this message is indicated by a high level at the output of the decoder 38, which places the RS flip-flop 46 in the zero state. The logic level from the inverse output of the RS flip-flop 51 enables the timer 45 to operate. This is the beginning of the first cycle of the exchange of priorities. The occurrence of a high level on the first timer 45 indicates the point in time when this device 1 / control should transmit a message with a tekup to them with a priority value prepared for data transmission. When a high level appears at the first output of timer 45, the logic unit levels from outputs 27 and 29 of encoder 14 allow information from counter 13 to be recorded into counter 16. In addition, a D-flip-flop 19. is set. A service block enters the first output of memory block 17 priority message (fig.Zv; with the priority value determined by the I current state of the counter 13. When a high level appears at the second input, the code converter 18 removes the level of the logical unit from the first output and starts the conversion of the blocks received on the the input input. The value of the counter 16 increases.-by one, the first output of the memory block 17 receives the end block, and the second output - the logic zero level. Upon completion of the conversion of the first block, the code converter 18 sets the first output level to logical one. This unit enters its second input through element I 20. Transducer 18 starts processing the next block (ending block) and sets the logical zero level at the first output. In this case, the value of counter 16 is increased by one at the second output of memory block 17 (the logical unity level appears), which places the D-flip-flop 19 in the zero state. Thus, when a logical unit appears at the fifth output of control unit 10, a message of the Priority type is transmitted to the communication line with a priority value determined by the state of the counter 13 and a set of valid priority values of the local control unit 1 {control. The end of the cycle of the exchange of priorities is indicated by the appearance of a (N + 1) -ro pulse at the second output of timer 45. At the same time, the output of counter 48 appears, the level of the logical unit, which, in turn, resets the RS-flip-flop 46.

During the cycle of the exchange of priorities, block 10 compares the received values of priorities with the current

This device’s priority is 1d. When receiving a message with a priority value greater than or equal to the current priority value of this device is about 5 ep

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1, —the control, the impulse from the output of the comparison node 37 resets the D-flip-flop 40. At the end of the priority exchange cycle, the level of the logical unit at the output of the Element I 41 indicates that the device 1 currently has the highest priority and may proceed to transfer data.

The data to be transmitted must be pre-recorded under the control of the central processor 5 in the COOT; there are no long-standing cells of the memory unit 17 according to the format (Fig. 3A) and the memory allocation table. Then, the counter address 13 must contain the cell address of the memory block 17, in which the service message block is stored with the priority value corresponding to the initial priority of the data recorded in the memory block 17.

The signal for starting data transfer is the occurrence of the logical unit level at the input of the AND 41 element. At that, the encoder 41 at the output 26 forms the address (A,) on which the first message block of the memory block 17 is recorded, and the levels of the logical unit at the outputs 28 and 29 encoders 14 provide the recording of the address from output 26 into counter 16, and also install D-flip-flop 19 into one state. At the output of element 20, a high level appears, indicating that the first block of the transmitted message arrived at the first output of block 17 of memory. The code converter 18 sets the zero to the first output and starts transmitting the first message block. The value of the counter 16 is increased by one and the second block of the transmitted message arrives at the output of the memory block 17. After finishing the processing of the first block, the converter-Tel 18 codes sets the level of the logical unit at the first output, which, through element 20, enters its second input, starts the conversion of the second block received from the output of memory block 17, and removes the level of the logical unit from the first output , etc.

Upon arrival at the output of the block 17 of the memory of the block of the ending of the message, a logic zero level is formed at its second output. After the conversion of the last block is completed, a high level appears at the second output of the memory block 17 and the D-flip-flop 19 is reset.

When one arrives at its input, the level of logical units removes the permitting level from the input of the AND 41 element to the time Tj (the time required to transfer the data and obtain confirmation from the receiver device). If during this time a confirmation is not received, then the level of the logical unit appears at the output of AND 41 and the message e is retransmitted. If, during time 3, the message is not transmitted and no acknowledgment of reception is received, the pulse from the output of timer 42 sets the RS-flip-flop 46 to one state and the next cycle of the exchange of priorities begins.

The fact that the confirmation of the evidence is evidenced by the occurrence of the logic unit level at the output of the decoder 38, which sets the RS flip-flop 46 to one, resets the t; 3 counts through the element 39 and enters the first input of the interface unit 8 This means that the data has been transmitted and a confirmation signal has been received.

If the local device 1 / control does not receive the right to transfer the prepared data on the results of the last exchange of priorities, the level of the logical unit from the first output of the control block 10 increases the value of the counter 13, thereby increasing the current value of the data priority. Counter value. 13 does not change if it is reset, i.e. This device 1 does not have data prepared for transmission, and if the counter 13 is completely full, i.e. data has the maximum possible for this device 1) priority value.

The occurrence of a logical unit level at the output of the comparison node 36 means that the data that is addressed to this control device is received, and an acknowledgment must be sent. The logical unit level at the second output of the interface unit 8 informs the central processor 5 that the received data can be read from the memory unit 12.

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At a high level at the input 23, the encoder 14 (table) provides the entry in the counter 16 of the cell address of the memory block 17 in which the first confirmation block is written. The transfer of acknowledgment is carried out in the same manner as the transfer of priority. The end of the acknowledgment transmission is the beginning of a new priority exchange cycle.

The system makes it possible to increase the efficiency of using the capacity of communication lines, since unproductive time losses are eliminated in the absence of information prepared for the transmission of information in one or several logical control units. In addition, the system allows you to organize the exchange of information in accordance with dynamic priorities.

Claims (4)

1. A control system of technological complexes containing N local control devices connected by nepBbiivffl inputs-outputs to the communication line, and the second inputs-outputs to the inputs-outputs of the corresponding communication devices with the object, This is because, in order to increase the capacity of communication lines by reducing the transmission waiting time for each local control device, an initial priority exchange device is introduced into it, which is associated with the output from the communication line. 2. The system according to claim 1, wherein each local control unit contains three memory blocks, a central processor, a control unit, two code converters, an interface unit, a system bus, an encoder, an input / output unit, a D-flip-flop , switch, And element, decoder, two pulse counters and a transceiver connected by the inputs-outputs with the first inputs-outputs of the device, the input with the first output of the first code converter, and the output with the input of the second code converter connected by the output to the input of the decoder and infor. to the second input of the memory block connected by the Reset input to the decoder output and to the first input the control unit, the Readout input — with the bus; Controls the output of the interface unit; the first information output — with the information input of the interface unit; and the second information output — with the second input of the control unit connected by the third input to the output of the first pulse counter and the first information output. to the switch input, the first output to the counting input of the first pulse counter, the second output to the reset input of the first pulse counter and the first input of the Service Requirement of the interface unit, the third output the home to the first input of the encoder and the second input of the Requirement for servicing the interface unit, the fourth output to the second input of the encoder, and the fifth output to the third input of the encoder connected by the first output to the second information input of the switch, the second and third outputs respectively to the first and the second uravlivayuschiesya and inputs of the switch, and the fourth output-- with the S-input of the D-flip-flop and with the enable input 1 of the second pulse counter connected by the installation input to the output of the switch, and the counting input to the first input of the first And the second input of the first code converter, connected by the first input to the output of the first element And connected by the second input to the output of the D flip-flop connected by C-input to the output control of the third memory block connected the first information input with the output of the second pulse counter, information : output - with the second input of the first code converter, and Recording input - with the installation input of the first pulse counter and the output bus of the interface unit, connected: with the input-outputs via the system bus with the input-outputs of the central processor, the first memory block, the unit input-output and e second input-output device. 3. The system of claim 2, wherein the control unit contains two comparison nodes, two RS triggers, a D flip-flop, two timers, a decoder, two OR elements, a pulse counter, two one-shot, three elements And, the inverter and the node of the initial installation, the same output with the S-input of the second : s,: -Y e 15 th 20 25 AOR - o Q - m  . - 50 55 RS flip-flop connected by an inverted output to the first input of the first timer, direct output to the first inputs of the first and second OR element, and R input to the decoder output, to the second input of the first OR element, and to the first input of the first AND element connected output to the second output of the unit, and the second input to the forward output of the D-flip-flop, to the input of the inverter and the first input of the second element I connected to the fourth output of the unit and the input of the second one-vibrator, the second input to the output of the second one-vibrator, and the third entrance - from the second input of the second element OR, with the inverse output of the first RS flip-flop and the first input of the third element AND connected with the second input with the output of the inverter, and the output with the first output of the block connected with the fifth output to the first output of the first timer connected with the second output with the counting the input of the pulse counter, and the second input - with the C-input of the D-flip-flop, With the input of the second timer and the direct output of the first RS-flip-flop connected by the S-input to the output of the first OR element, and the R-input to the output. the counter and mylcov, connected by a setup input to the output of the second element OR, the output of the second timer connected to the third input of the first OR element, and the first input of the unit to the input of the first one-oscillator connected to the first inputs of the first and second comparison nodes and the first input of the decoder, connected by the second input with the second inputs of the first and second comparison nodes with the second input of the unit connected by the third output to the output of the first comparison node, and the third input to the third input of the second comparison node is connected output with R-input D-flip-flop. 4. The system of claim 1, wherein the initial priority exchange device comprises a trigger element, a NOT element, a shift register, two permanent memory blocks, two AND elements, two OR elements, a code converter and a transmitter connected to the output device, and the input to the first output of the converter (code generator, connected by the second output to the control input the shift register associated with the shift (named after the input with the output of the element NOT, the first output with the first inputs of the first AND and OR elements, and the second output with the second input of the first OR element and the first input of the second AND element connected with the output to the first input the second element OR, connected by a second input with an output the first element is AND, and the output is to the first input of the code converter connected by the second input to the output of the first element OR, the first and second blocks of the permanent memory are Dami first and second elements And, and the input element is not connected to the output element start. 1 Any block 1 (service) b / 1OKP- 1 /Data b / ioH {(c / {/ e5ftt} {l /) b / ioM f (s / g / me6mbBS)  Z Blon Fi.5