SU1430987A1 - Device for measuring credibility of digital magnetic recording - Google Patents

Abstract

The invention relates to the field of instrumentation, in particular to a technique of digital magnetic recording, and can also be used in digital information transmission systems. The goal is to increase the accuracy of measurements. The device contains connected in a defined way a clock pulse generator 9, three switches 4, 11, 14, two code generators 5 and 46, a recording amplifier 15, a playback amplifier 2, magnetic recording and reproducing heads 16 and 1, display unit 6, four binary counters 8, 19, 44, 45, shift register 43, twelve elements AND 29-40, comparison block 18, three flip-flops 20, 21, 22, two counting-indicator units 13 and 47, four decoder 12, 17, 41 and 42, five elements OR 24-28, a stop signal generating unit 10, a clock synchronization unit 3, sign indicator 48. Improving the accuracy of the measurement of the reliability of a digital magnetic recording is achieved by introducing a second reference code generator 46, which ensures accurate detection of errors in the event of a failure in cyclic synchronism reproducible from a magnetic carrier and reference measurement sequences of pulses that occur during long-term deposition and account for accurate measurement of phase slippage in a wide range, by determining the temporal mismatch of the occurrence of cyclic sync pulses sov with first and second code generators. 2 Il. i (L

Description

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WITH about with

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The invention relates to instrument making, and to the technique of magnetic recording, and can be used to measure the reliability of digital magnetic recording.

The purpose of the invention is to improve the measurement accuracy.

FIG. 1 and 2 shows a block diagram of the device.

A device for measuring the reliability of a digital magnetic recording contains serially connected playback head 1, amplifier-driver 2, clock synchronization unit 3, first switch 4 and first code generator 5, the outputs of which are connected to the corresponding inputs of the display unit 6 and multiplexer 7, the control inputs connected through the first counter 8 to the second input of the first switch 4, the second input of which is connected to the generator 9 clock pulses, the third input to the input of the unit 10 forming the signal stop the media and through serially connected second switch 11 and first decoder 12 to the outputs of the first counting and indicating unit 13, the output of multiplexer 7 is connected via the third switch 14 and the recording amplifier 15 to the recording head 16, the second input of the third switch 14 is connected to the first input of block 6 indications; as well as the second decoder 17, the comparison unit 18 and the second counter 19, four flip-flops 20-23, five elements OR 24-28, twelve elements AND 29-40, the third and fourth decoders 41 and 42, the shift register 43, the third and fourth counters 44 and 45, the second code generator 46, the first output of which is connected through the first element AND 29, the first element OR 24, the comparison unit 18 and the shift register 43 to the first input of the second element 30, the second input of which is connected to the first the input of the first trigger 20 and through serially connected second t a rigger 21 and a second decoder 17 with inputs of the second counter 19 connected by a control input to the first control inputs of the first and second generators 5 and 46, to the output of the shaping amplifier 2, to the second input of the second trigger 21, to the first inputs of the third and fourth elements And 31 and 32, the outputs of which are connected respectively to the first and second inputs of the second element OR 25, the output connected to the second input of the unit 18 comparison; the second counting and indicating unit 47, the first input of which is connected through the third element OR 26, the third trigger 22, the fifth element AND 33, the sixth element AND 34 and the third decoder 41 to the outputs of the third counter 44, the control input connected to the first output the second generator 46 codes; sign indicator 48, connected via a serial connection

The fourth element OR 27, the fourth trigger 23, the seventh, the eighth elements And 35 and 36, the fourth decoder 42 and the fourth counter 45 to the first output of the first generator 5 codes, while the output of the block 3 clock synchronization is connected to the counting inputs of the second, third and fourth counters 19, 44 and 45, to the synchronous input of the second code generator 46, to the second inputs of the shift register 43, the first and second calculating and indicating units 13 and 47, the output of the last of which through the fifth element OR 28 is connected to the first inputs of the ninth and ten addition elements and 37 and 38, the last of which is connected to the second input

5 to the second output of the second generator 46 of codes, to the second inputs of the first, third, sixth and eighth elements And 29, 31, 34 and 36, the third inputs of the last two are connected to the control output of the first generator 5 of codes, with the second inputs of the fourth,

0 of the ninth element And 32, 37 and through the eleventh element And 39 with the second input of the first element OR .24, the control second input of the first generator 5 codes is connected to the first output of the first 5 trigger 20, to the third input of the fourth and to the second input of the eleventh elements Both 32 and 39, the third input of the latter is connected to the second output of the third switch 14, the second output of the first trigger 20 is connected to the second control input of the second

0 of the code generator 46 and to the third inputs of the first and third elements I 29 and 44, the second input of the first trigger 20 is connected to the third output of the first switch 4, the third input of which is connected to the control output of the first counting-indicating unit 13, the second input connected to the output of the second element And 30, the third control inputs of the first and second generators 5 and 46 codes are connected to the outputs of the tenth and ninth elements And 37 and 38, respectively, the first h the second inputs of the twelfth element And 40 are connected respectively to the outputs ter and its fourth de schifratorov 41 and 42, and the output - to the second input of the fifth OR gate 28, the output - to the second and fourth inputs of the sixth and

5 of the eighth elements AND 34 and 36, the outputs of which are connected respectively to the second inputs of the fourth and third triggers 22 and 23, the first outputs of which are connected to the second inputs of the third and fourth elements OR 26 and 27, respectively, and the second outputs to the second inputs, respectively. mi the fifth and seventh elements And 33. and 35.

The device works as follows.

When recording a measurement waveform in the form of a continuously generated pseudo-random sequence of pulses, the generator is synchronized with 5 codes of 5

Dits on each clock interval, set by the generator 9 clock pulses. In this mode, the magnetic recording head 16 records a magnetic signal on the magnetic carrier, which is fed to the input of the recording amplifier 15 from the serial output of the code 5 generator through multiplexer 7 and the third switch 14. The recording of the measuring sequence in the form of repeating code words with a length equal to the number of cells Shift register generator 5 codes used to detect "difficult combinations of characters, is as follows. A multiplexer 7, controlled by the first counter 8, pushes all the cells of the generator 5 codes with a frequency specified by the generator 9 clock pulses. In this case, code generator 5 is in the mode of generating a pseudo-random sequence, and its synchronization is performed by a clock signal generated at the control output of the counting-indication unit 11. This ensures that the same short combination is repeated many times with a length equal to the number of cells of the generator’s 5-shift register .

In the error measurement mode, the measurement signal reproduced by the magnetic reproduction head 1, amplified and formed by the shaping amplifier 2, fed to the first control input of the code generator 5, performs its cycle phasing. In this case, the potential output of the reference measurement signal from the first output of the generator 5 codes through the third switch 14, the element I 39 and the element

OR 24 to the first input of the comparator unit 18, to the second unit of which, through the element 32 and the element OR 25, a reproducible measuring signal is supplied. Comparative unit 18 performs elementwise analysis of it. Selected faults occurring in the process of recording and reproduction are fed to the input of the counting-indicating unit 13 through the shift register 43 and the second element And 30. The counting-indicating unit 13 provides

calculation and indication of the measured value, which is triggered in the absence of phase slip. Phase slips are measured as follows. Loop sync. 1s, arriving at the elements And 33 and 35, trigger the triggers 22 and 23.

No factor in error.

Defining a predetermined threshold value of the error ratio, when the device operates in the "difficult combinations" detection mode, performs the decipher 12, the inputs of which are connected to the outputs of the counting and indicating unit 13. The threshold is selected by connecting one of the outputs of the decipher 12 through the second switch 11 to block 10 generating a media stop signal. Wherein

50

When a forward cyclic sync pulse arrives from a 46 code generator through an AND 33 element to a trigger 22, it is triggered, the signal from its second output blocks And 35, and from the first

blocking of the output 55 output is also carried out through the OR element 26 of the clock pulses to the first generator 5 to the counting-display unit 47, which measures and indicates the value of the phase slip in the clock interval.

Dov, and the display unit 10 indicates the detected 1; 1 "difficult combination.

 in a way.

When precipitations appear in a reproducible measuring signal, the flow of information signals to the control input of the counter 14, which nulls it at the control input, is stopped, and a signal is triggered at the output of the decider 17, which switches the trigger 21. The potential that occurs at the output of the trigger 21 blocks the I 30 element, prohibiting the signal errors at the input of the counting and indicating unit 13,

to the second input, which is the counting input of trigger 20, and causes its switching. In this case, the signal arising at the first output of the trigger 20 is fed to the second input of the control generator 5 codes,

inhibits the input of the reproduced signal and blocks the signal from the control output. The signal from the second output of the trigger 20 permits the arrival of the reproduced signal to the input of the generator 46 codes. Its cyclic phasing is carried out after the end of the fallout. In this case, at its first output, a signal arises that permits the input to the first input of the comparison block 18 of the reproduced signal through the AND 31 element and the OR 25 element,

to the second input of the unit 18 comparison - the reference signal through the element And 29 and the element OR 24.

Thus, after the termination of the fallout, code generator 46 is in cycle synchronization with the input signal. With

In this case, the code generator 5 continues to function and it turns out to be possible to measure the "slippage from the temporal mismatch of the cyclic clock signals extracted from both sequences of binary symbols. This happens next0

For the first code 5 generator, cyclic sync pulses are allocated by a counter 45 and decipher 42, and for a code generator 46, a DVOICHN1M counter 44 and a decoder 41. The cyclic sync signals pass to the phase slip measurement node through their inputs 34 and 36 when they have inputs the enabling signals from the outputs of the generators 5 and 46 codes and from the element 40,

50

When a forward cyclic sync pulse arrives from a 46 code generator through an AND 33 element to a trigger 22, it is triggered, the signal from its second output blocks And 35, and from the first

Upon subsequent arrival of the cyclic sync pulse from the first generator 5 codes to the second input of the third trigger 22, it switches to the initial state, which causes a corresponding signal removal from the input of the calculating and indicating unit 47, which indicates the measured phase slip after that. At the same time, a signal is generated at its control output, which triggers the triggering of the elements 37 and 38, the signals from the outputs of which arrive at the third control inputs of the generators 5 and 46 of the codes. The feedback circuit of the cyclic phasing node of the code generator is opened, the first control input of which receives the resolving potential from one of the outputs of the trigger 20. Thus, one of the generators is prepared for a new cycle phasing upon the occurrence of a subsequent fallout.

When a leading cyclic sync pulse arrives, extracted from a sequence of binary symbols from the generator outputs 5 codes, the trigger 23 triggers it. At the same time, the signal from the second output of the trigger 23 blocks the element I 33, prohibiting the passage of a delayed cycle sync pulse extracted from the sequence generated by the code generator 46 to the trigger input 22. The signal from the first output of the trigger 23 is fed to the input of the counting-indicating unit 47 through the element The SLI 26 and the character indicator 48 through the SLI 27 element. The retarded cyclic clock pulse arriving at the second input of the trigger 23 switches it to the initial state and the phase slip measurement ends. The character indicator 48 provides an indication of the phase slip sign, taking into account which of the sequences is used to measure the reliability after the end of the fallout. This makes it possible to determine the sign of the drift of the clock synchronization unit of the magnetic recording apparatus under study.

Claims (1)

Invention Formula A device for measuring the reliability of a digital magnetic recording, containing successively connected a reproduction head, an amplifier-form and a router, a clock synchronization unit, the first switch and the first code generator, whose outputs are connected to the corresponding input.m of the display unit and multiplexer, whose control inputs connected via the first counter to the second switch output, the second input of which is connected to the clock generator, the third input to the input of the carrier stop signal generation unit - and through a serially connected second switch and the first decipher to the outputs of the first counting and indicating unit, the multiplexer output is connected via a third switch and a recording amplifier to the recording head, the second input of the third switch is connected to the first input of the display block, and the second decipher, block Comparison and second counter, characterized in that, in order to improve measurement accuracy, four triggers, five elements of SLI, twelve elements P, third and fourth decipherors, a shift register, three are entered into it. tiy and fourth counters, the second code generator, the first output of which is connected through 5 connected in series the first element P, the first element of the PLP, the comparison unit and the shift register to the primary input of the second element P, the second input of which is connected to the first input of the first motor igger and through the serially connected second  a trigger and a second deflector with the outputs of a second counter connected by a control input to the first control inputs of the first and second code generators, to the output of the amplifier of the world-wide, to the second input of the second trigger, to the first inputs of the third and fourth elements P, the outputs of which connected, respectively, to the first and second inputs of the second OR element, the output connected to the second input of the B.Yuka comparison, the second counting-indicative unit, the first input of which is under, t SLI, the third trigger, the fifth element And, the squite element And and the third decoder to the outputs of the third counter, which controls the input connected to the first 5 output of the second code generator, the indicator indicator, the input connected via serially connected fourth ILP element, fourth trigger, seventh, eighth elements P, fourth decoder and Q is the fourth counter to the first output of the first code generator, while the output of the clock synchronization unit is connected to the counting inputs of the second, third and fourth counters, to the synchronous input of the second code generator, to the second inputs of the shift register, 5 of the first and second counting and indication blocks, the output of the last of which is connected via the fifth element of the ILP to the first inputs of the ninth and tenth elements of AND, the second input of the last is connected to the second output of the second code generator, to the second 0 inputs of the first, third, sixth and eighth elements P, the third inputs of the last two are connected to the control output of the first code generator, with the second inputs of the fourth, ninth elements P and through the eleventh element P with the second input  the first element of the PLC, the controlling second input of the first code generator is connected to the first output of the first trigger, to the third input of the fourth and to the second input of the eleventh And elements, the third input of the last is connected to the second output of the third switch, the second output of the first trigger is connected to the second control to the input of the second code generator and to the third inputs of the first and third elements I, the second input of the first trigger is connected to the third output of the first switch, the third input of which is connected to the control, it to the output p the first- countable the indicator unit, a second input connected to the output of the second AND gate, the third control inputs of the first and second code generators connected to the outputs of the tenth and ninth elements And, respectively, the first and second inputs of the twelfth element And are connected respectively to the outputs of the third and the fourth decipherors, and the output to the second input of the fifth element OR and to the fourth inputs of the sixth and eighth elements And, the outputs of which are connected respectively to the second inputs of the fourth and third triggers, the first outputs of which connected to the second inputs of the third and fourth elements OR, respectively, the second outputs to the second inputs of the fifth and seventh elements AND, respectively. srigL