SU1429287A1 - Synchronous detector - Google Patents

Abstract

The invention relates to electronic measuring devices in automation. The purpose of the invention is to improve the demodulation accuracy with random phase shifts. The device contains a dynamic storage device 1, a pulse shaper 2, a differentiating circuit 3, a full-wave rectifier 4, r-p of the reference signal 5, a phase shifter 6. A phase detector 7, a zero-comparator 8 and a D-flip-flop are introduced to achieve the target. 9. The zero-comparator 8 in this circuit is essentially a driver of wide (half-period duration) pulses from the output voltage of the phase shifter 6. If the random phase shift between the input and reference signals does not exceed t90, then using the phase detector 7 and phase shifters schatel compensated 6 and D-inputs of the flip-flop 9 is maintained initially set offset phase input signals. If the phase shift exceeds t90 º, but does not reach fl80, then the stable operation of the device is ensured by D due to the long duration (equal to the half-period of the input signal) of the enabling pulses that are input to the D input of the D flip-flop. 9. 3 Il. (L

Description

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The invention relates to electronic measuring devices in automatics and is intended to convert high-frequency amplitude-modulated signals of various sensors into low-frequency ones, perceived by inertial measuring or performing devices.

The purpose of the invention is to improve the accuracy of demodulation during random phase shifts.

Fig. 1 shows a structural electrical circuit of a synchronous detector; figure 2 shows the time diagram of his work; on fig.Z - transfer characteristic of the phase shifter.

The synchronous detector contains a dynamic memory device (CDZU) 1, a driver of 2 pulses, a differentiating circuit 3, a full-wave rectifier 4, a generator 5 of the reference signal, a phase shifter 6, a phase detector 7, a null comparator 8, a D-trigger 9.

Synchronous detector. Works as follows.

The input signal (Fig. 2a) is fed to the signal input of the DZU 1 and at the same time to the circuit consisting of sequentially connected shaper.

2 pulses differentiating circuit

3 and full-wave rectifier 4 The main purpose of this circuit is to form narrow pulses from the input signal

at the moments of transition of the input voltage through zero (Fig. 2b). These pulses are fed to the clocking C-input of the D-flip-flop 9, which is triggered if at this time a high potential is set at its D-input (FIG. 2d). A high potential appears on the control input of the DZU 1 (fig.2d), which permits the passage of the input signal at the moment of its crossing through zero. The next pulse at the C input of the D-flip-flop 9 returns the D-flip-flop to the initial state, since by this time the zero potential is established at its D-input. As a result, the control of the input of the DZU 1 also supplies a zero potential, which prohibits the further passage of the input signal through it. Thus, D-trip er 9 allows only one positive or negative half-wave of the input signal to pass through the DZU 1, and at exactly those moments

time when the input signal changes its polarity and is almost zero in magnitude. As a result, at the output of the synchronous detector, a slowly varying signal is emitted, with a signal of positive or negative polarity, which carries information about the amplitude variations of the input signal (Fig. 2e). Changing the polarity of the output signal of the synchronous detector is usually caused by a jump-like change in the phase of the input signal by 180. That during normal operation of the circuit indicates that the value of the measured physical parameter at the given moment is equal to its reference value. Stable operation of the synchronous detector is possible under the condition that the signals at the inputs of the D-flip-flop 9, formed from the input and reference signals (Fig.26), have between them a phase shift not exceeding ± 90 °, with the actual phase shifts of the input signal relative to the reference, Oscillation in the range 0. t 180. For this, the input signal of the synchronous detector is supplied to the first input of the phase detector 7, and to the second input -. a reference signal of the same frequency from the reference signal generator 5. The output voltage of the phase detector 7 is fed to the control input of the phase shifter 6, to the signal input of which the voltage of the reference signal generator 5 is applied. The output of the phase shifter 6 produces an alternating voltage shifted in phase relative to the reference value is determined by the level of the output voltage of the phase detector 7. The zero comparator 8 in this circuit is a driver of wide (half-period) pulses from the output voltage phase shifter 6. If under the influence of any perturbing factors there appear significant phase shifts of the input signal relative to the reference signal, then first of all they are converted with a phase detector 7 into a proportional voltage at its output that goes to the control INPUT of the phase shifter 6. Shift The phases of the output voltage of the phase shifter 6 vary linearly depending on the control voltage only up to 90, and then remain constant (Fig. 3). So, if a random phase shift between input 10

Claims (1)

the detector, respectively, successively connected Fort Schroweler yoguls, a differentiating circuit and a full-wave rectifier, as well as a reference signal generator and a phase shifter, characterized in that, in order to ensure demodulation accuracy during random phase shifts, a phase detector, zero a comparator and a D-trigger, the input of the pulse generator and the first input of the phase detector are connected to the input of the synchronous detector, and the output of the phase detector is connected through a series-connected phase shifter and The ul-comparator is connected to the information input of the D-trigger, the clock input of which is connected to the 2Q stroke, a full-wave counter, the claims of the invention and the output are connected to the control input of the dynamic memory device, a synchronous detector containing solids, and the generator output is a dynamic memory device The reference signal is connected to the second signal input and the output of which is in the 25 input of the phase detector and is signaled by the input and output of the synchronous input of the phase shifter, signal and reference signal does not exceed 190 °, then it is compensated with the help of phase detector 7 and phase shifter 6, and the initially set phase shift of the incoming signals is stored at the inputs of D-flip-flop 9. If under the action of disturbances the phase shift between the input and reference signals exceeds ± 90 °, but does not reach tlSO, then the stable operation of the synchronous detector is ensured due to the long duration (equal to the half-period of the input signal) to the cut of the pulses received at the D input D- trigger 9. Timing diagrams for phase shift dc / 135 ° are shown in fig.2zh, s, and k, l, m respectively. venno. 1429287 ten 15 2Q avk Nacha / ttHtiu shift Random ssvig / / - / / / L ; I I I / r I / TV e and uh  e m rti m m I ru rti TTi i rtl t u Beginning cdSui fo-90 ®L.rTVLScnychain --t VlV nn H M MM M -i i / i; rl J J --J I I I fur 11 L- .. I I I I I 1 I I I  G 111t  VLJr} I-J-J-L i / / L -J F ; I I I / r I / TV t Chnychay --t  t / iput.5