SU1429285A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and provides an increase in the spectral purity of the output signal. The digital frequency synthesizer contains a clock pulse generator 1, a frequency divider with variable coefficient. division (DPKD) 2, block. continuous memory 3, frequency setting block 4, accumulating adder (NS) 5, code converter 6, memory register 7, DAC 8, low pass filter 9. In the digital frequency synthesizer, a linear-step approximation of the sinusoid with uniform quantization of the level and non-uniform time-slicing. The slope of each linear region of the approximation is provided by varying the frequency supplied to the HC 5. The transition from one linear region to another occurs when the coefficients change. divisions of the PDKD 2, the values of which are recorded in the block of permanent memorization 3. Upon completion of the enumeration of all values of the coefficient. dividing the DPKD 2, as a result of which a sinusoid is formed in the first quadrant, the converter 6 is switched, and it starts to pass to its output the additional code 5. The result is a reverse order of enumeration of all coefficients. division DPKD 2, which ensures the formation of a sinusoid in the second quadrant. With the establishment of the sign bit HC 5 in 1, a similar formation of neg. half wave sinusoids. 1 il. (L 4 to from th 00 SP

Description

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The invention relates to radio engineering and can be used to obtain reference frequencies in communication systems.

The purpose of the invention is to increase the spectral purity of the output signal.

The drawing shows a structural electrical circuit of a digital frequency synthesizer.

The digital frequency synthesizer contains a generator of 1 clock pulses, a divider 2 frequencies with a variable division factor (DPD) t, block 3 permanent memory (BOD), block: 4 frequency settings, accumulating; adder 5, converter 6 codes memory register 7 ty, digital-to-analog converter (D / A converter) 8, low-pass filter 9 (LPF),

Digital frequency synthesizer works as follows.

The frequency setting block 4 is installed at the same time. With this, the 6 code converter again ensures that the direct code of accumulating adder 5 is passed to its output. Thus, the formation of the third and fourth quadrants of the sinusoid is similar to the formation of the first and second quadrants. After the formation of a sinusoid period, the process is repeated. The code from the output of the converter 6 codes enters the input of the register 7 of the memory, where it is entered by the pulses arriving at its clock input from the output of the PDKD 2. The register 7 of the memory carries amplitude

At the input, a sum-25 accumulating value of the curve approximating the sitor 5 code determines the value of the output frequency of the synthesizer. Accumulating adder 5 for each pulse arriving at its clock

nusoid. From the output of memory register 7, the signal is fed to the input of the DAC 8, and then to the low-pass filter 9, which prevents the signal from entering the frequency F

nusoid. From the output of memory register 7, the signal is fed to the input of the DAC 8, and then to the low-pass filter 9, which prevents the signal from entering the frequency F

input, sums the input code from output-30 to the output of the digital synthesizer private, as a result, the output code grows linearly. Upon reaching the outgoing code of the accumulating adder 5 of the beginning of the following linear section of the approximated sinusoid, which corresponds to a change in the code at the higher bits of the outputs of the accumulating adder 5, a new code is extracted from the BPZ 3. The new code value provides a change in the frequency at the output of the DPCD 2 in accordance

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then you.

Thus, in the digital synthesis of the frequency torus, linear-stump pench approximation of a sinusoid occurs with a uniform quantization over the level and uneven in time. The slope of each linear section is provided by changing the frequency Fi entering the accumulating adder 5. The transition from one linear section to another takes place by changing the coefficients of the PDKD-2 specified by the BPZ 3.

with the equality F Fc / K, where

frequency output DPKD 2; f frequency generator 1 clock pulses;

..- tion of the sinusoid in the second quadrant. At the end of the formation of the last linear section of the second quadrant of the approximated sinusoid, the sign bit of the accumulating adder 5 is set to one, which corresponds to the formation of a negative half-wave of the sinusoid.

At the same time, with this, the converter of the 6 codes again ensures that the direct code of the accumulating adder 5 is transmitted to its output. Thus, the formation of the third and fourth quadrants of the sinusoid is similar to the formation of the first and second quadrants. After the formation of a sinusoid period, the process is repeated. The code from the output of the converter 6 codes enters the input of the register 7 of the memory, where it is entered by the pulses arriving at its clock input from the output of the PDKD 2. The register 7 of the memory carries amplitude

values of a curve approximating a sinusoid. From the output of memory register 7, the signal is fed to the input of the DAC 8, and then to the low-pass filter 9, which prevents the signal from entering the frequency F

to the output of the digital synthesizer

to the output of the digital synthesizer

then you.

Thus, in a digital frequency synthesizer, a linear-step approximation of a sinusoid occurs with a uniform level quantization and non-uniform in time. The slope of each linear section is provided by changing the frequency Fi input to the accumulating adder 5. The transition from one linear section to another is carried out by changing the division coefficients of the PDKD-2 specified by BPS 3.

Claims (1)

K. - division ratio of DPKD 2 into 45 claims. 1st plot approximation. As a result, the rate of accumulation of the second code of the accumulating adder 5 is changed and the following linear portion of the approximated sinusoid is formed. After the enumeration of all the values of the DPKD 2 K division factor recorded in BPS 3, the code converter 6 switches and begins to pass on its output the additional code of the accumulating accumulator 5. This entails the inverse order of enumeration of all coefficients K, which ensures the formation of a digital frequency synthesizer containing a series-connected frequency setting unit, accumulating a Q adder and a code converter, a serially connected memory register, a digital-to-analog converter and a low-pass filter, and a clock generator unit and 55 memory, where the output of the sign bit of the accumulating adder is connected to the input of the sign memory register, the clock input of the memory register is connected to the digital frequency synthesizer containing the series-connected frequency setting unit, the accumulator and the code converter, serially connected register memory, digital-to-analog converter and low pass filter, as well as a clock and block generator permanent memory, where the output of the sign bit of the accumulating adder is connected to the input of the sign of the memory register, the clock input of the memory register is connected to the clock input of the accumulating adder, characterized in that in order to increase the spectral purity of the output signal, a frequency divider is introduced with a variable division factor, the output of which is connected to the clock input of the memory register, the output of the clock generator is connected to the input of a frequency divider with a variable division factor, higher The bit outputs of the code converter are connected to the upper bit inputs of the memory register and the address inputs of the permanent memory unit, the lower bit outputs of the code converter are connected to the lower bit memory inputs of the memory register, the bit outputs of the permanent memory unit are connected to the corresponding bit positions variable frequency division divider with single inputs