SU1427580A1 - Adaptive corrector of inter-symbol interference - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to reduce the tuning time and improve the accuracy of the correction by adapting the tuning step. The corrector contains delay lines 1 and 15, adder 3, adjustable amplifiers 4, integration of voltage 5, multiplier 6 and 14, regenerator 7, subtraction blocks 8 and 11, quadrant 9, integrator 10 with reset, rectifier 12 and block division 13. The multiplication in the multiplier 14 of the error signal generated at the output of the subtraction unit 8, and the constant adaptation signal (adjustment step) generated at the output of the division unit 13, provides a change in the speed and accuracy of the correction depending on the quality of the correction, 1 Il.

Description

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The invention relates to telecommunications and is intended to correct intersymbol interference in data transmission devices.

The purpose of the invention is to reduce the setting time and improve the accuracy of the correction.

The drawing shows an electrically structural diagram of an adaptive intersymbol interference corrector.

Adaptive intersymbol interference corrector contains p auxiliary delay line 1 consisting of (nt) delay elements 2, adder 3, n adjustable amplifiers A, n integrating elements 5, n multipliers 6, regenerator 7, subtraction unit 8, quadrator 9, integrator 1 with a reset, an additional subtracting unit 11, a rectifier 12, a dividing unit 13, an additional multiplier 14, an additional delay line 15.

Adaptive corrector intersymbolistic interference works as follows.

The input signal is fed to the input line 1 delay, as well as to the input of the first adjustable amplifier 4 and to the first input of the first multiplier 6. Through the elements 2 2 of the delay line 1 the signal goes to all other adjustable amplifiers 4 and to the first inputs of all other multipliers 6 The control of the adjustable amplifiers 4 is conducted by a signal from the outputs of multipliers 6 through the integrating element 5. From the outputs of all adjustable amplifiers 4, the signals are fed to the inputs of the adder 3, the output of which is the output of the equalizer. At the same time, a corrector control signal is generated. The signal from the output of the adder 3 is fed to the first input of the subtraction unit 8, the second input of which receives the evaluation of the transmitted data symbol from the output of the regenerator 7. At the output of the subtraction unit 8, the difference between the signal and its evaluation (i.e., an error signal) is generated is fed to the input of the additional multiplier 14 and the first and second inputs of the quadrant 9. The square from the error signal is fed to the input of the integrator with a reset 10. The integration time is chosen equal to M clock interval

transmitted data characters. The evaluation signal of the mean square error E from the output of the integrator 10 with the reset 10 is fed to the first input of the additional subtractor 11.

At the output of the additional block 11, a signal is generated corresponding to the difference between the signal E and

the same signal delayed by M clock intervals by means of an additional delay line 13.

Permanent adaptation (adjustment step) (U of the device is formed at the output of dividing unit 13 according to the following rule

pN E,

The operation of calculating the modulus is necessary in order to exclude the possibility of the occurrence of negative values, since, by definition, UN-O, This operation is performed by the rectifier 12.

The multiplication of the error signal generated in the code of block 8 and the signal UNc of the output of block 13, carried out in an additional multiplier 14, provides a change in the speed and accuracy of the correction depending on the quality of the correction.

Claims (1)

Invention Formula Adaptive intersymbol interference corrector, containing n integrating elements, n a lateral delay line, whose taps are connected respectively to the inputs n of adjustable amplifiers and to the first inputs n of multipliers, the outputs of each of which are integrated through the 1st element of the adjustable amplifiers, the outputs of which through the series-connected adder and regenerator are connected to the first input of the subtraction unit, to the second input of which the output of the adder is connected, which differs so that, in order to reduce the tuning time and increase the accuracy of the correction by adapting the tuning point, between the output of the first block in reading and the second input n of the variables. residents were introduced in series a quad, integrator with a reset, additional delay line 1427586 ki, an additional subtraction unit, a multiplier multiplier, to the input of which is a rectifier, a division unit, and the output of the subtraction unit is additionally connected