SU1425773A1

SU1425773A1 - Apparatus for synchronizing playback of digital magnetic recording

Info

Publication number: SU1425773A1
Application number: SU874217718A
Authority: SU
Inventors: Федор Андреевич Цвентух; Владимир Кузьмич Ушаков; Александр Алексеевич Юрасов; Борис Васильевич Новиков
Original assignee: Институт кибернетики им.В.М.Глушкова
Priority date: 1987-01-09
Filing date: 1987-01-09
Publication date: 1988-09-23

Abstract

Изобретение относитс к магнитной записи, а именно к устройствам дл .синхронизации воспроизведени цифровой магнитной записи. Целью изобретени вл етс повышение достоверности 1воспроизвбдени информации за счет улучшени параметров системы ФАПЧ устройства. Цель достигаетс путем помехоустойчивого декодировани промежутков синхронизации и использовани режима частотной автоподстройки дл ускорени отработки реальной частоты и фазы входных сигналов воспроизведени . Устройство содержит первьй мультиплексор 1, ЛС- триггер 7, два D-триггера 9,10, ключи 12,13 зар да и разр да, ФНЧ 14, генератор управл емый напр жением 15, делитель 16 частоты, Т-трйггер 17, элемент 4 задержки, элемент 2И-НЕ I1, а также введенные в него второй мультиплексор 18, регистр сдвига 2, первый 5 и второй 8 инверторы, элемент 2И 3 и детектор 6 нулей, которые соединены между собой и с указанными функциональными элементами соответствующими св з ми. I э.п. ф-лы, 3 ил. i (f)The invention relates to magnetic recording, in particular, to devices for synchronizing the reproduction of digital magnetic recording. The aim of the invention is to increase the reliability of reproducing information by improving the parameters of the device PLL. The goal is achieved by noise-resistant decoding of the synchronization gaps and using the frequency-controlled mode to accelerate the processing of the real frequency and phase of the input playback signals. The device contains the first multiplexer 1, LS-trigger 7, two D-triggers 9,10, keys 12,13 charge and discharge, low pass filter 14, generator controlled voltage 15, frequency divider 16, T-trigger 17, element 4 delays, 2I-NOT I1 element, as well as the second multiplexer 18, the shift register 2, the first 5 and the second 8 inverters, the 2I 3 element and the detector 6 zeros, which are interconnected and with the indicated functional elements by connections, introduced into it. I ep f-ly, 3 ill. i (f)

Description

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Claims

Claim

1. A device for synchronizing the playback of digital magnetic recordings containing the first multiplexer, delay element, JK trigger, first and second D triggers, 2I-NOT element, charge and discharge keys, low-pass filter, voltage-controlled oscillator, frequency divider, The T-trigger, as well as the input of the recording clock, the input of the playback data, the input of the playback permission, the output of the data window and the output of the data signal, the input of the clock pulses and the input of the playback data of the device are connected respectively to the first and second the inputs of the first multiplexer, the output of which is connected to the input of the delay element, the direct output of the first ^ -trigger is connected to the first input of the 2INE element, the second input of which is connected to the direct output of the second D-trigger, the information input of which, the information input of the first D-trigger and J- the input of the JK trigger is interconnected and connected to the unit potential bus, the low-pass filter input is connected via the charge key to the direct output of the first D-trigger, and through the discharge key is connected to the inverse output of the second D-trigger, the input to the initial installation of which and the input of the initial installation of the first D-trigger are interconnected, the output of the low-pass filter is connected to the input of a voltage-controlled generator, the output of which is connected to the input of the frequency divider, the synchronizing inputs of the JK-trigger and the first D-trigger are interconnected, the output element 2 AND NOT under- (keys ,. to the input of the initial setup of the IR trigger, the K input of which is connected to the zero potential bus, which means that, in order to increase the reliability of decoding the reproduced information, the first and second inverters, the second multiplexer, element 2I, the shift register and the zero detector are introduced the output of which is connected to the first input of element 2I, the second input of which, the first input of the zero detector and the information input of the shift register are interconnected and connected to the input of the playback permission of the device, data input voltage is connected to the input of the synchronization of the shift register and to the second input of the zero detector, the third input of which is connected through the first inverter to the output of the shift register, the initial setting input of which is connected to the output of element 2I, the other output of the shift register is connected to the control input of the first multiplexer, the output of the delay element is connected to the output of the device data signal and to the synchronizing input of the JK trigger, whose inverse output is connected through the second inverter to the inputs of the initial setup of the first and second D-triggers jers, set input 1 JK-flip-flop, the second output shift Giustra D _r, the initial input tired _;

the new T-flip-flop and the output of the sign for synchronization of the device are interconnected and connected to the control input of the second multiplexer, 10 the second input of which is connected to the first output of the frequency divider and the synchronizing input of the T-flip-flop, the output of which is connected to the output of the data window device, the second output 15 of the frequency divider is connected to the third inputs of the second multiplexer, the output of which is connected to the synchronization input of the second D-trigger.

2Q 2. Device pop. 1, characterized in that the zero detector contains a T-trigger, three delay elements, an adder modulo two, two D-flip-flops and a counter, while

25, the first input of the zero detector is connected to the input of the initial setup of the T-trigger,. whose synchronizing input, the synchronizing inputs of the first D-trigger and counter are interconnected and connected to the second input of the zero detector, the inputs of the first and second delay elements are connected respectively to the direct and inverse outputs of the T-trigger, and their outputs are connected respectively to the first and second the inputs of the adder modulo two, the output of which is connected to the input of the third delay element, the output of which is connected to the information

4G input of the first D-flip-flop, the output of which is connected to the control input of the counter and to the installation input in »1 of the second D-flip-flop, whose inverse output is connected to the output

45 zero detector, the third input of which is connected to the input of the initial installation of the second D-flip-flop, whose inverse output is connected to the input of the initial • counter installation, output

5Q which is connected to the synchronizing input of the second D-trigger, in-; whose formation input and the information input of the counter are connected to the zero potential bus.

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