SU1425681A1 - Device for checking linear digital systems - Google Patents

Abstract

The invention relates to computing and can be used for the functional control of binary linear digital systems. The purpose of the invention is to reduce the control time. The device contains two signature generators 1, 2, two modulo two accumulators 3, 4, comparison block 5, memory block 6, counter 7, element OR 8, two delay elements 9, 10, trigger 11, fault indication block 12. The memory block 6 of the transfer function coefficients of the monitored linear digital system, together with modulo-two accumulators from the modulator, corrects the input and output signatures of the monitored system so that these signatures become equal. Based on the result of comparing these signatures, it is concluded that the system is healthy. Due to this, the functional control of the system is provided directly in the process of its operation. 1 il. o (C (U)

Description

Vh, inf. afxl

8th inf. 8 (x)

The invention relates to computing and can be used for the functional control of binary linear digital systems.

The aim of the invention is to reduce the monitoring time of linear digital systems operating in continuous operation mode that prevents the system from being stopped for JQ testing, and to increase the reliability of the information processed by the diagnostic object.

The drawing shows a block diagram of a device controlling linear digital systems.

The device contains the first 1 and second 2 signature generators, the first 3 and second 4 modulo two accumulators, block 5. Comparison of 20 I signatures, memory block 6, counter 7, I element OR 8, first 9 and second 10 I delay elements trigger 11, block

12 fault indication, object

13 control, informational inputs

we, and b (x) is a polynomial of degree at most K, corresponding to the output sequence, then

B (x) a (x). 0 (x)

or

B (x) .a (x) -b ..-.:, .-, 1 + og, x + ...

or

b (x) (1 + ot, x + ... bi x) a (x) ((5 ", X + ... + x). (1)

Consider the polynomial c (x) ccx)

Y G (x), where G (x) y, + y, x + ... + + 3-, x or c (x) JoC (x) + + y, c (x) x + ... + j nc (x) x (2)

Since the signature shaper

and quintril, ishuiAlchschiipski 25 register with reverse sa - 14 and 15. first 1 and second 2 forms) used to obtain

binary sequence signatures is also a linear digital system and the superposition principle is fulfilled for it, then the 30 signature of the sequence corresponding to the polynomial c (x) will be equal to the sum of two signatures modulo

Signature telles synchronizing: input 16 and device reset input 17,

the first 18, the second 19, the third 20 outputs of the memory unit.

i The principle of operation of the device is as follows.

I The transfer function of an n-dimensional linear digital system is written as follows:

: - lJi - + -: L- ± LlllL,

: 1 + oi, x + ...

 sequences, members of formula (2).

For the sake of consistency, formula (2) is conveniently presented in the form of a table, where each i-row is a sequence with (x) x (multiplying by x corresponds to adding i before the lower digits of the sequence i) zeros) In the column, the coefficients are written; with power x.

where "xL;

/ 3; e o, i, o o, p.

If a (x) is a polynomial of degree K (k), the corresponding input information of the linear digital system. Below is a table for cases c (x) of degree 5 and the polynomial G (x) 1 +

we, and b (x) is a polynomial of degree at most K, corresponding to the output sequence, then

B (x) a (x). 0 (x)

or

B (x) .a (x) -b ..-.:, .-, 1 + og, x + ...

or

b (x) (1 + ot, x + ... bi x) a (x) ((5 ", X + ... + x). (1)

Consider the polynomial c (x) ccx)

Y G (x), where G (x) y, + y, x + ... + + 3-, x or c (x) JoC (x) + + y, c (x) x + ... + j nc (x) x (2)

 sequences, members of formula (2).

For the sake of consistency, formula (2) is conveniently presented in the form of a table, where each i-row is a sequence with (x) x (multiplying 0 by x corresponds to adding i before the low-order bits of the sequence i) the column contains the coefficients Y; with power x.

+ x + x

C4 C,

Each coefficient Xj of a polynomial, equal to one, identifies a string-sequence in the table, the signature of which is necessary to know to determine the signature of the sequence (cXx).

All these necessary signatures can be obtained on one signature generator as information is received from (x), fixed by their coefficients Y | polynomial, given in order of decreasing degrees. From the table it can be seen that in order to obtain the signature of the K-first bits of the sequence c (x), the first

. y (Cg, 1 O, K)

Then, in accordance with formula (1), the operation of the operational control system of linear digital systems with the transfer function o6vi, ero of the form will be described by the logical equation

21, (t .;) mod 2

i “h

 Zlp ..; 2,

where X and X 2 are the states of the first and second signature drivers, respectively; The memory block contains coefficients of the polynomials corresponding to the numerator and denominator of the transfer function of the linear digital system,

In general, information in the coefficient of memory function block 6 of the transfer function is entered as follows. On the first k-n-1 addresses, zeros are programmed on all outputs, from the k-n-ro addresses on the K-th through the first and second

Cj

Cj

with,

ABOUT

one

O .0

eleven

with the arrival of the k-n-ro bit of the sequence c (x), the signature is fixed. For example, the signature of the first six bits of a sequence c (x) is equal to the sum modulo two sequence signatures

20

C C (j, CQ, SdSd s, CQ,

If we designate the signature of the sequence corresponding to the polynomial c (x) through y (Ce, 1 O, K), and the state of the shift register with feedbacks at time t; as x (t;), then

(r

; x (q;) mod 2.

the outputs are programmed to denominator coefficients oi; and numerator ft; the transfer function of a linear digital system is in the order of 35 degrees. At the Kth address on the third approach, a unit is programmed corresponding to the Comparison impulse arriving at signature comparison block 5. Below are the tables for programming ROM for the general case and for a specific example in which a linear digital system with a transfer function is taken as the object of control.

J

45

Q (x)

X + x

1 + X + x

to the input of which the sequence is received and the sequence is taken from the output. For of this case, n 4, k 5.

Zeros are programmed for the first k-n-1 5-4-1-0 addresses. Starting with the k-n 5-4-1 addresses on the first and second outputs, the coefficients of the denominator and numerator of the transfer function 0 (x) are programmed, respectively:

514256816

0 (x) ..x l.x + O.x + Q.x -h 1.x + 1.x

Coefficients of the transfer numerator By k 5-address. On the third output

4P functions (7Р fio -01010. The coefficient is 5 programmed to one, corresponding to the denominators of the gear ratio to impulse Comparison.

functions about 0 0-11001.

Outputs 3 (20) 2 (19) 1 (18)

000

000 ...

o00

about

about

45

The first and second accumulative adders modulo two can be implemented on 1K-triggers with a reset, included d as triggers with a counting input of T-type (I- and K-inputs are connected together) "The size of accumulating adders modulo two, t" e. the number of triggers is equal to the size of the shift registers with feedback.

The device works as follows.

Initially, the first 1 and second 2 signature generators, the first 3 and second 4 modulo two accumulators, the binary counter 7, the control object 13, which represents the linear digital system along an external reset circuit, are set to the zero initial state, after which the first driver 1 signatures ready to receive incoming information input 14 output sequence 50

00000000o about o

00000001о 1

00000010o 11

00000011000

00000100- 1 o

00000101 1 o 1 00 o

five

d

0

of the controlled linear digital system, and the second shaper of 2 signatures is ready to receive the input sequence a (x) of the controlled linear digital system arriving at its information input 15.

The first k-n-1 clock cycles of the first 1 and second 2 signature generators verify the incoming to their information inputs 14 and 15 of the output and input information of the linear digital system.

In block 6 of the memory of the coefficients of the transfer function of the linear digital system, zeros are written at the first k-n-1 addresses.

Starting from the k-n-ro clock, the block 6 of the memory of the coefficients of the transfer function on the first 18 and second 19 outputs begins to reset the signals Reset 1 and Reset 2, corresponding to

to uL and and to; the denominator and numerator of the transfer function of the linear digital system, arriving at the first 3 and second 4 modulo two accumulators allowing the passage of the next signatures into them,. removed from the first 1 and second 2 signature drivers. Thus, in the first 3 and second A, on the accumulators, modulo-two adders will be received in signat

rs equal to the sums bi; x (t) .; ) mod 2

  n

about

And (tk-0 ° 2 respectively.

ittl

With the arrival of the k-ro clock pulse, the block 5 of the memory of the coefficients of the transfer function on the third 20 output results in a comparison signal, which through the second delay element 10 enters the gate input of the block 5

tc by the formational input of the trigger, about t - l and h. You need it so that, in order to reduce the monitoring time, the device contains a second signature generator, two modulo-two accumulators and a memory block, with the information input of the device connected to the information INPUT; the second signature generator and is the output of the device

comparison of signatures, allowing comparison of signatures obtained in the first 3 25 connection of the information input and the second 4 modulo-two accumulating adders (thus, equality (3) is checked). In case of their inequality, unit 5 with 30

35

 Signatures produce a malfunction signal of the monitored linear digital system, which, via trigger 11, enters the malfunction indication unit 12. By comparison, through the first delay element 9, the OR element 8 resets the device to the zero state, after which it is ready to receive the next data word. The second delay element 10 is in order for the control signal to be received. The comparison arrives at the signature comparison unit 5 with some delay relative to the signals arriving at the OS. The tonal inputs of the unit 5 are the comparison of the signals of the natures, which increases the reliability of the performance of the comparison. The first delay element 10 serves to delay the zeroing of the blocks 1,2, 3,4,7 for the duration of the operation

yes of the monitored system, the first input of the element Sh1I is connected to the reset output of the device for connecting the monitored input of the monitored system, the clock input of the device is connected to the counting input of the counter, the synchronous inputs of the first and second signature drivers and the clock output of the device for connecting the same input of the monitored system, the information input of the first the signature generator is the device input for connecting the output of the monitored system, the output of the OR element is connected to the reset inputs of the first and a second shapers signature and the first and second accumulator modulo two, the group of information outputs of the first and second signature generators are respectively connected to groups of information inputs of the first and second accumulator modulo two groups of outputs which are connected respectively to the first and

, t, / rid 13D H JJlrn: i «1L CL rl. - comparison in signal 5 comparison unit to the second group of information inputs round, comparison unit, group of outputs count. The proposed device allows to realize continuous functional control without stopping the object for testing, to increase the reliability of data processing results, to increase the survivability of the object of control.

Claims (1)

Invention Formula A control unit for linear digital systems containing the first signature generator, a comparison unit, two delay elements, an OR element, a trigger and a counter, the device reset input connected to the first input of the OR element, the second input and output of which are connected respectively to the output of the first delay element and to the reset input of the counter, the output of the comparator unit is connected to the informational input of the trigger, about t - l and h. You need it so that, in order to reduce the monitoring time, the device contains a second signature generator, two modulo-two accumulators and a memory block, with the information input of the device connected to the information INPUT; the second signature generator and is the output of the device 0  connecting information input yes of the monitored system, the first input of the element Sh1I is connected to the reset output of the device for connecting the monitored input of the monitored system, the clock input of the device is connected to the counting input of the counter, the synchronous inputs of the first and second signature drivers and the clock output of the device for connecting the same input of the monitored system, the information input of the first the signature generator is the device input for connecting the output of the monitored system, the output of the OR element is connected to the reset inputs of the first and a second shapers signature and the first and second accumulator modulo two, the group of information outputs of the first and second signature generators are respectively connected to groups of information inputs of the first and second accumulator modulo two groups of outputs which are connected respectively to the first and i - The sensor is connected to the group of address inputs of the memory block, the first, second and third information outputs of which are connected respectively to the resolution input of the second accumulating modulo two adder, and the resolution input of the first accumulating 9142568110 modulo-two adder and the input of the delay element, the synchronous input of the trigger-second delay element, the output of the bark and the gate input of the comparator unit are connected to the input of the first circuit.