SU1422381A1 - Pulse shaper - Google Patents

Description

(21) 4213197 / 24-21.

(22) 02.02.87

(46) 09/07/88. Bnsh. Number 33

(71) Belarusian State University. IN AND. Lenin

(72) N.V. Naumov, V.V. Butsky, S.S. Vetokhin and N.B. Kireev

(53) 621.374 (088.8)

| (56) USSR Copyright Certificate 711671, cl. H 03 K 5/01, 1977. USSR Copyright Certificate No. 1072257, cl. H 03 K 5/02, 1982 ..

(54) PULSE FORMER

(57) The invention relates to a pulse technique and can be used in processing and information acquisition devices for selecting the first and last pulses in a burst, when the number of pulses in each burst differs from the number of pulses in the previous one. The purpose of the invention is to increase the reliability of the driver. The pulse shaper contains the triggers 1, 2, the element AND-NOT 3, the first element I. 4, the first inverter 5, the clock bus 6, the input bus 7, the second element AND 8, the element OR 9, the second inverter 10. The purpose of the invention is achieved by that two keys are stored in the pulse shaper with the storage of the control signal 11 and 12, the first, and the second output buses .13 and 14. The introduction of two keys with the storage of the control signal 11 and 12 makes it possible to reliably form a packet of pulses on the output bus 13 relative to the original for the period of the pulse in the pack, and n output bus 14 are formed first and last pulses of the burst, which are shifted relative. motionless, for the duration of the pulses in the packet. 2 Il.

S

(L

73

1

; The invention relates to a pulse technique and can be used in processing devices and the collection and information to highlight the first and last pulses in a bundle when the number and relieves in each bundle differ from the number of pulses in the previous one.

The aim of the invention is to improve the reliability of the former. A: FIG. 1 shows a functional diagram of a pulse former; FIG. 2 is a diagram of his work.

The pulse shaper contains the first 1 and second 2 triggers, the element AND-NOT 3, the first element AND 4 ,, the first inverter 5; t act bus 6, input bus 7, the second element is AND 8, element OR 9, the second inverter 10,

: two keys 11 and 12 with control signal memorization, first 13 and wto; Rui 14 weekend tires.

The first input element AND-NOT 3 connect

With the clock bus bis, the first input of the first element AND 4s is the second input of the AND-3 element connected to the input bus 7 and through the first inverter 5 to the second input of the first element AND 4. The output of the second element AND 8 is connected to the first input of the element OR 9, the second input of which is connected to the input of the second inverter 10. The first 11 and the second 12 are entered into the shaping unit (the keys with a memory of the control signal; the control input of the first key 11 is connected to the clock input of the second trigger 2 and connected to the forward the output of the first trigger 1, and the switching input of the first Key 11 is connected to the clock bus 6. The output of the first switch 11 is connected to the switching input of the second key 12, to the first input of the second element I 8 and connected to the first output bus 13, the control input of the second key 12 is connected to the inverse output of the second trigger 2, single the input of which is connected to the output of the second inverter 10. The information inputs of the first and second triggers 1 and 2 are connected to the common bus. The output of the NAND element 3 is connected to the single input of the first trigger .1, the clock input of which is connected to the output of the first element IZ, and inverse The output is connected to the second-1 input of the second element AND 8, the output of the second key 12 is connected to the second input of the element OR 9, the output

50

five

0

5 0 5 Q

which is connected to the second output bus 14.

Each of the keys 11 and 12 entered into the driver (more precisely, the pulse keys with a memory of the control signal) is a device that switches the pulse from the input to the output using a control signal and remembers the control signal at the moment the switching pulse starts, resulting in a change in the signal control after the start of action and during the action of the switched pulse does not change the switching. The keys 11 and 12 can be performed, for example, by a known scheme.

The pulse shaper operates as follows.

In the initial state in the absence of a burst, the trigger 1 is in the zero state (Fig. 2e), since its C-input receives clock pulses from bushes 6 (Fig. 2a) through the open valve 4 (Fig. 2d). At the same time, there are no pulses at the output-key 11 (Fig. 2e), and, consequently, at the output of the key 12 (Fig. 2h). The state of flip-flop 2 does not matter here, since it does not affect the passage of pulses through CL1C (h 12,

Packet pulses arrive synchronously with clock pulses, and the leading edges of the burst pulses Coincide in time from the front “5I fronts like that”. Tov pulses.

With the arrival of a burst of pulses on the input bus 7 (Fig. 2b), the first negative pulse at the output of the elec. COP-AND-3 (Fig. 2c) sets trigger 1 to one state.

When fulfilling the conditions

; te chi

where Lz, - the duration of the input pulse; TI is the duration of the clock pulse; at the C input of trigger 1, there is a zero level over the entire duration of the burst. The moment of occurrence of the unit level at the direct output of trigger 1 is delayed relative to the front of the third clock pulse (Fig. 2a, the delay is composed of delays of the AND-HE element 3 and trigger 1), which comes from the bus from the bus to the switch input of the key 11. As a result of switching

key 11 does not change i. at its output will remain zero. A positive difference at the direct output of trigger 1 sets trigger 2 to the zero state (Fig. 2g) or confirms its zero state. Thus, at the inputs of the control keys 11 and 12, unit levels are set. In this case, clock pulses are allowed, starting from the fourth (in Fig. 2a), through the key 11 to the output bus 13. The first pulse from the output of the key 11 passes from the input of the key 12 to its output and sets trigger 2 through the inverter 10 condition. At the same time, at the control input of the key 12, a zero level is established that prohibits the passage of the second and subsequent keys from the output of the key 11 through the key 12. As a result, the output of the key 12 generates a pulse that is the first of the packet to shift by the period of the pulses in the packet. This pulse through the element OR 9 passes to the output bus 14 (Fig. 2k).

When the burst ends, the output of the element AND-NO 3 PI in

thirty

35

40

the rotor 5 is set to single levels. At the time of arrival of the next clock pulse (the seventh one in Fig. 2a), trigger 1 is set to the cool state. Since a change in the signal at the direct output of flip-flop 1 from one to zero occurs after the start of the seventh clock pulse Bdro, this pulse travels to the output of the key 11, and the subsequent clock pulses do not pass. As a result, at the output of the key 11 the packet of pulses is shifted with respect to the initial one for the period of the following pulses in the packet. A single signal appearing at the inverse output of trigger 1 (when the trigger is set to zero) permits the last pulse from the packet formed at the output of the AND key to pass through AND 8 (Fig. 2i) and further through OR 9 to the second 50 output of the first ele 5a I, and inverse output pin 14. A pulse to the output output is connected to the second input

element And 8 is the last of the second element And the output of the second

packs shifted for the period of the key following is connected to the second input of the pulses in the pack. With the installation of the OR trigger, the output of which is connected to state 1 to the zero state, the shape-55 is connected to the second output bus.

Pulse shaper, content-. eager first and second triggers, the element AND-NOT, the first input of which is connected to the clock bus and the first input of the first element AND, the second input of the element IE-PE is connected to the input bus and through nepBhCi the inverter is connected to the second input of the first element AND, the second element AND the output of which is connected to the first input of the OR element, the second input of the OR element is connected to the input of the second inverter, which is different in that, with the purpose of increasing reliability, two keys are inserted in it that stores the control signal, the control input of the first key is connected with t such as are for input of the second flip-flop and connected to the forward vkodu first flip-flop, the input comments -tatsi first key COR key to a clock bus, the first switch output connected to the input of the switching of the second switch; with the first input of the second element I and connected to the first output bus, the control input of the second key is connected to the inverse of the second flip-flop, the single input of which is connected to the output of the second inverter, the information inputs of the first and second flip-flops are connected to the common bus NOT connected to the single input of the first trigger, the clock input of which is connected to

The detector returns to its original state and is ready to receive the next lean burst of pulses.

I

As a result, a packet of pulses is formed on the output cord 13, shifted relative to the initial pulse for the period I1, in the packet, and on the output 14, the first and last pulses of the burst are shifted relative to the initial pulse on the period of pulse in the packet.

the output of the first element 5a And, and the inverse output is connected to the second input

Claims (1)

Invention Formula The pulse shaper containing the first and second triggers, the AND – NE element, the first input of which is connected to the clock bus and the first input of the first element AND, the second input of the AND – PE element is connected to the input bus and through the nepBhCi inverter is connected to the second input of the first element And, the second element AND the output of which is connected to the first input of the element OR, the second input of the element OR is connected to the input of the second inverter, which is different in that, with the purpose of increasing reliability, two keys are inserted with the memory of the control signal control input or the first switch is connected to the clock input of the second flip-flop and connected to the forward vkodu first flip-flop, the input comments -tatsi first key COR key to a clock bus, the first switch output connected to the input of the switching of the second switch; with the first input of the second element I and connected to the first output bus, the control input of the second key is connected to the inverse of the second flip-flop, the single input of which is connected to the output of the second inverter, the information inputs of the first and second flip-flops are connected to the common bus, the output of the AND-NO element connected to the single input of the first trigger, the clock input of which is connected to iLZ.2