SU1420615A1 - Apparatus for monitoring multichannel magnetic recording unit - Google Patents

Abstract

The invention relates to instrumentation. The purpose of the invention is to reduce the monitoring time with per-channel error analysis. To do this, the device containing the device 1 magn. records, generator 2, shaper 3 codes, error extraction block 4, time division block 5, element OR 6, error counter 7, strobing unit 8, code converter 9, address triggers 10, memory block 11, display unit 12. counter 13, control elements 14-16, AND element 17, start trigger 19, prohibition elements 20, 21, OR elements 22, 23, one-shot 25, 26, delay elements 27, 28, prohibition element 29, strobe block 18, divider 30 frequencies, elements 31 and 32, counter 33, decoder 34 and trigger 35. The device operates automatically in the channel error separate filling mode, while the channel error memory cycle includes the sequential generation of a pulse for setting the address of the RAM block 11, the rewriting pulse in the counter 13 and pulse count and a last write the new contents of the counter included in the channel memory unit 11. The outputs of flip-flops 10 perebirayuts all channel addresses memory unit 11, and the zeroing of each channel is produced by counter 13 to zero the content of the operation element 14 signal. 3 il. & (L

Description

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The invention relates to instrumentation, in particular to a magnetic recording technique.

The purpose of the invention is to reduce the monitoring time with per-channel error analysis.

FIG. 1 shows a functional scheme of the device; in fig. 2 - timing diagrams illustrating the principle of its work; in fig. 3 - device code converter in expanded form, option.

A device for monitoring errors of a multichannel magnetic recording apparatus 1 comprises a generator 2, a shaper 3 codes, a multichannel error isolation block 4, a time division block 5 (errors of different channels), a multiple-input element OR 6, an error counter 7, the first block 8 gating, code converter 9, address triggers 10, operational block 11, block (channel) indication 2, first binary counter 13, first 14, second 15 and third 16 control elements, first element 17, second (optional) gating unit 18, trigger 19 start a, the first 20 and second 21 prohibition elements, the first 22 and second 23 OR elements, the first 24, the second 25, the third 26 one-shot, the first 27 and the second 28 delay elements, the third (additional) prohibition element 29, frequency divider 30, the second (additional) element And 31, the third (additional) element And 32, the second (additional) binary counter 33, the decoder 34, the erase trigger 35 and the trigger 36 are executed.

FIG. 1, a dashed line indicates a block 27 of the memory channel number indication, which can be connected to the outputs of section 34, but which is not the first element for the device.

The first output (low-frequency) of the generator 2 is connected to the clock input of the imaging unit 3 of the code, the outputs of which are connected to the inputs of the recording channels of the magnetic recording apparatus 1, to the outputs of the playback channels of which the inputs of the multichannel error extractor 4 are connected.

The outputs of block 4 of the output 01bibok are connected to the inputs of block 5 for time division, the reference input of which is connected to the second output (high-frequency) of generator 2 and to the input of frequency divider 30. The outputs of the temporary separation unit 5 are connected to the inputs of the multi-input element OR 6 and to the signal inputs of the gating unit 8. The output of the multi-input element OR 6 is connected to the counting input of the error counter 7 and to the first input (clocking input C) of the D-flip-flop 19. At the information input D of this three tera, a high level of voltage "1, is constantly applied (this link is not shown). The trigger trigger 19 is connected to the signal input of the prohibition element 20, the output

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which is connected to the first input of the element OR 22 ,, the output of which is connected to the input of the one-shot 24, the output of which is connected to the lock input of the RAM block 11, to the input of the delay element 28 to the signal input of the prohibition element 21, the inverse output of which is connected to the input of the single-vibration 25 The inverse output of which is connected to the input of the one-shot 26, the output of which is connected to the second blocking input of the prohibition element 20 and to the first input of the element OR 23, the output of which is connected to the input of the delay element 27, the output of which ene with counting input of the binary counter 13 and a read-write control input of the RAM memory 11. The current output of the one-shot 25 is connected to the second (set to zero) input of the start trigger 19 and to the control input of a group of installation inputs of the binary counter 13. The outputs of the gating unit 8 are connected respectively to the outputs of the gating unit 18 and to the inputs of the code converter 9, the outputs of which connected to the first (installation in one state) inputs of D-flip-flops 10 addresses, the unit outputs of which are connected to the address inputs of the RAM 11. The output of the delay element 28 is connected to the interlock input of the prohibition element 29, with the second input of the And 17 element and with the second (clocking) inputs C of the trigger 10 address. The information inputs of the D-flip-flops 10 addresses are constantly applied to a low voltage level "O (this link is not shown). The output of the frequency divider 30 is connected to the first input of the AND 31 element, the output of which is connected to the third input of the OR element 22 and the first input of the AND element 32, the output of which is connected to the counting input of the binary counter 33, the bit outputs of which are connected to the inputs of the decoder 34, the outputs which from the second to the penultimate one is connected to the signal inputs of the gating unit 18. The first output of the decoder 34 in the device is not used. The output of the control element 16 is connected to the first (clocking) input C of the D-flip-flop 35, the output of which is connected to the second input of the OR element 23 and to the second input of the AND element 31. The output of the control element 14 is connected to the second blocking input of the prohibition element 20, to the input blocking element 21 prohibition, with the input of the installation in the zero state of the binary counter 13, with the second (informational) input of the D flip-flop 35, with inverse meters installation into the zero state input of the binary counter 33, with the input of the blocking prohibition element 29 which exit th connected to the input gating gating unit 8, and a first input of AND eleglenta 17, whose output is connected to the input gating unit 18 gating. The outputs of the control element 15 are connected to the installation inputs of the flip-flop 36, the output of which is connected to the second input of the OR element 22 and to the second input of the AND 32 element. The outputs of the RAM block 11 are connected to the inputs of the channel 12 O channel display unit and the group of the binary inputs counter 13, the outputs of which are connected to the information inputs of the 1 1 RAM.

The last output of the decoder 34 is connected to the erase trigger 35, which is set to the zero state. To the outputs of the decoder 34, a block 37 of the indication of a meter of channel memory can be connected.

The specific performance of individual nodes and blocks of the proposed device is as follows.

Generator 2 contains its own typical autogenerator of a continuous sequence of pulses with a frequency of 500 kHz and a frequency divider controlled by speeds (according to the working speed of movement of the magnetic carrier of the controlled magnetic recording device 1) at its output. The signal from the output of the controlled frequency divider (the first output of the generator 2) as a recording clock signal with the corresponding frequency is fed to the input of the imager 3 codes. The high frequency signal (500 kHz) directly from the output of the autogenerator (second output 1 of generator 2) is fed to the input of the reference signal of the time division block 5 and pa input of the frequency divider 30.

The shaper 3 of the code generates a test signal in the form of a pseudo-random sequence of characters in a known way on the basis of the shift register covered by logical feedback through a modulo two. The pseudo-random signal from the output of the shift register in the BVN form (without returning to zero) of the signal (in the BVN signal "O corresponds to a low level, and" 1 - a high voltage level) together with the recording clock signal is fed (if necessary, through matching devices ) to the input of each drip of the recording-reproduction of the apparatus to be controlled 1.

Each recording channel of the apparatus 1 contains a BVN signal converter into a signal with relative phase shift keying of a rectangular nonsunde (OFM signal) and a BVN signal recorder of the BWN signal recording current method without returning to zero. The recording of signals is made by multi-speed. Block. Magnetic recording heads on magnetic; The recording is classified as sequential or asynchronous, since the recording channels between themselves (and the playback channels between themselves) in apparatus 1 are not connected. Each playback drip of apparatus I contains a magnetic reproducing head (combined in

mnogodoro; -; echio.m b.ukuke ma1nit1 1kh go.yunok reproduction, am11. 1uit.1no-often1h; s1 | n phase-frequency correctors, formally. and. rectangular OF.M signal of recall, synchronizer and demodulator of the OFM signal, which deals with the conversion of the OFM signal into BVN. From the output of each channel of the playback apparatus 1 reproduced test signal p

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BVN form and clock signal is | -o

the same channel is fed into a multi-canal. yuk 4 to the entrance of a separate kana.pa, shadow of errors.

Multichannel block 4 opiKi ky contains kapal1a1 error selection n

5 number equal to the number of channels of the recording-reproduction of the controlled apparatus 1. Each selection channel contains a shift register with the corresponding code-forming shift register for mi, t 3 code taps, which

0 through the first modulo-two adder connected to the first input of the second modulo-two adder, the second input of which is connected to the information input of the shift register and the information output of the output channel 5 of the product. A replay clock signal is applied to the clock input of the shift register. The scheme describes a co6oii, well-known error detector, which works according to the principle of verifying a reproducible pseudo-random psu, one on the right () its

0 code set in shift register understated. When playing the test CH.MBO.KI, at the output of the second moderator, 1K) two, a high level is set, iorned "1. The output signal of the second side modulo two (in the form of sig5 on, that BVN) is gated to synchronize, play back on the gating element connected between the output of the second modulo two and the output of this error extracting channel. From the output of each channel, a dedicated and a 01 outdated bob is 4 Nm 11y.: I, - s of errors and a separate input of the block 5 of time separation of pulses O1bibok of different channels is available. yuv

The time division block 5 contains a distributor of pulses, the input of which is connected to the input of the reference signal of block 5, the first triggers - Tpnn-epi) of storing the received errors supported by the first inputs to the first; - nal; {th block 4 is divided by the 1st I, and the first is the first, the first, and the first are, the first, T1, 1 of the survey, the first inputs of which are distributed to the outputs of the distribution. 1 mpu, the second triggers are issued (for the account), and the second e, the cops And the second e..1e) are oyros. For example, the first inputs of the second elements AND

5 connect s1 to the outputs of the distributor of 1M-pulses with a shift relative to those corresponding to the first elements of the I, inputs - from the output. second triggers, and you

moves - with the first inputs of the second triggers and with the second inputs of the first triggers, the outputs of which are connected to the second inputs of the first triggers, the outputs of which are connected to the second inputs of the first elements And, the outputs of which are connected to the second inputs of the second triggers and connected to the outputs of block 5.

Counter 7 errors - counter with a digital indicator of the number of counted total errors.

Gating blocks 8 and 18 are assembled on the basis of building inverters.

The code converter 9 is shown in FIG. 3 in expanded form and contains eight five input elements OR. This code converter converts a single 24-bit code (the possible number of code combinations at the converter input is 24) into an 8-bit code (impulse) of the memory channel address and is intended for a control device of a 24-channel magnetic recording device 1. The columns of binary digits to the left and right of the converter 9 in FIG. 3 is clear: when the error pulse of the first recording-playback channel arrives (the first column on the left), the first (out of 24) input of the converter 9 generates a binary code 00000001 (the first column on the right) of the address of the first memory channel and so on. d.

Triggers 10, 19 and / 35 - /) are triggers.

The channel error indication unit 12 consists of eight LEDs connected through appropriate matching amplifiers to the eight outputs of the main memory unit 11.

Element 14 controls the toggle switch.

Elements 15 and 16 of the control buttons. At the inputs of control elements 14-16 (not shown), a high level of "1.

Elements 20, 21 and 29 of the prohibition pass the signal applied to their signal inputs, if there is no control signal, the signal at the inputs of blocking these elements. The prohibition element does not transmit a signal if a control signal is given to its blocking input. The prohibition element is a two-input (or three-input) I element, one of the inputs (or two of the three inputs) of which is connected to the input (or inputs) of the prohibition blocking through the inverter (or two inverters respectively).

The duration of the output pulse of the single-vibrator 24 is approximately equal to 500 ns. The duration of the output pulses of the one-vibrators 25 and 26 are equal to one another and equal to approximately 740 ns.

The delay elements 27 and 28 are four inverter connected in series.

The decoder 34 - three consistently working decoder, the inputs of which

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connected to the outputs of the three alternately operating counters, forming a binary counter 33.

Binary counter 33 has an inverse setup input, i.e., this counter is set to the zero state when there is no signal at its setup input.

The performance of the remaining elements of the device is well known.

The device works as follows.

The test signals generated by the shaper 3 of the code in the form of pseudo-random symbol sequences are fed to the inputs of the recording channels (not shown) of the monitored magnetic recording apparatus 1 and then recorded in it on a magnetic tape (not shown). The reproduced signals from the outputs of the playback channels (not shown) of the apparatus 1 are fed to the inputs of the multichannel error extraction unit 4. The error pulses from the outputs of the error isolation block 4 are fed to the inputs of the block 5 for time separation of the error pulses of different channels.

The presence of block 5 is related to the fact that the error pulses of different channels of recording-reproduction of apparatus 1 allocated by independent channels of block 4 can coincide in time. To ensure that each of these error pulses is counted by one error counter 7, such pulses (coinciding in time) of different channels must be separated in time. This is accomplished by block 5 of spacing in time of the pulses of the errors of different channels.

The output signals of block 5 are combined with the multi-input element OR 6, the total error signal of all channels from the output of which is fed to the counting input of the counter 7 errors.

The remaining elements, nodes, and blocks of the device are designed to store the number of errors for each recording / reproduction channel of apparatus 1 separately.

The device works automatically in the mode of separate accumulation of channel errors. In this case, the toggle switch 14 must be turned off, i.e. the signal at the output of control element 14 is absent in the channel-by-channel error accumulation mode.

Let the pulse be at the first output (diagram 1 in Fig. 2) of time division block 5. This error pulse arrives at the first input of the gating unit 8, and also passes through the element OR 6 (the output total error signal of which is shown in diagram 3, Fig. 2) and is fed to the input of the error counter 7, as well as to the first input of the start trigger 19 and switches it.

The output signal (positive voltage difference) trigger trigger 19

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passes through the element 20 of the ban and the element OR 22 on the launch of the one-shot 24.

The output pulse of the address (diagram 4 in Fig. 3) of the one-shot 24 is fed to the lock input of the RAM block 11 and to the input of the delay element 28. The address pulse from the output of delay element 28 (diagram 5 in Fig. 3) is fed to the inputs of address triggers 10 and brings them to the initial zero state, and also passes through the prohibition element 29 to build gating unit 8. As a result of the last at the first input of block 8 and, accordingly, a pulse is formed at the first input of the converter 9 of the code.

The code converter 9 is designed so that the error pulses of each recording / reproducing channel of apparatus 1 are automatically set at the outputs of the trigger 10 to the eight-digit code of their own, i.e., corresponding to the given channel, address.

In the presence of a pulse at the first input of the converter 9 of the code, a pulse is formed at its first output (Fig. 3), i.e. a parallel binary (pulse) code 00000001 is generated at the outputs of the converter 9. In accordance with this, the first trigger 10 of the switch and A potential code 00000001 is set at the address inputs of the memory block 11, i.e., the triggers 10 store the output code of the converter 9. Each address code includes the corresponding memory channel (for writing or reading channel errors) of the block 11 perativnoy memory.

The change of addresses of the RAM block 11 is performed during the pulse at the blocking input of this block.

Thus, the error pulse of the first recording / playback channel of apparatus 1 included the address of the first memory channel of block 11.

Next, you need to increase the contents of this memory channel by one. To ensure this, a binary counter 13 is used, which is controlled as follows.

The output pulse of the address of the one-shot 24 also passes through the element 21 of the ban on starting the second one-shot 25, which is triggered (triggered) to the fall of the address pulse.

The output positive impulse of the single-vibrator 25 (diagram 6 in Fig. 2) —the overwrite pulse — comes from its direct output to the second input of the start trigger 19, and resets it to its initial state, and also goes to the control input of the group of the installation counter 13 .

In this case, a binary eight-digit number is recorded in the binary counter 13, which is present during the operation of the rewriting pulse at the outputs of the block 11

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memory. This binary number corresponds to the number of error pulses of the first recording-playback channel that was recorded in the first memory channel before the arrival of this error pulse of the first channel. The RAM unit 11 at this time is in read mode — a low signal level (Figure 7 in FIG. 2, which shows the output counting pulse of the delay element 27).

The duration of the output pulse of the single-vibrator 25 is determined by the required time (speed) of writing in the binary counter 13 the output information of the operational memory unit II.

Thus, each output pulse of the one-shot 25 — a rewrite pulse — overwrites the contents of this memory channel of block II into a binary counter 13.

On the falling edge of the negative output pulse of the one-shot 25, a third one-shot 26 is started.

The output pulse of the one-shot 26 blocks the element 20 of the ban, and also passes through the element OR 23 to the input of the element 27 of the delay.

The delay element is required to introduce a delay between the end of the installation of the number in the binary counter 13 and the operation of this counter at the counting input.

The counting and recording pulse from the output of the delay element 27 is fed to the counting input of the binary counter 13 and to the write control input by reading the memory unit 11, which during the operation of this pulse is transferred to the write mode. During the action of the leading edge of the counting and recording pulse, the contents of the binary counter 13 are incremented by one and immediately written to this memory channel of the block 11.

This completes the increase in the content unit of the first memory channel — the error memory channel of the first recording-playback channel.

Let follow the wils error pulse at the 24th output (diagram 2 in Fig. 2) of the time division block 5. This pulse arrives at the 24th input of the gating unit 8, and also passes through the OR 6 element and is counted by 7 total errors. The pulse of the error of the 24th recording-playback channel from the output of the element OR 6 also goes to the first input of the start trigger 19 and switches it. The output signal of the trigger 19 passes through the prohibition element 20, the OR element 22 and starts the one-shot 24. The output pulse of the address of this one-shot is fed to the lock input of the main memory unit 1I and after some time comes from the output of the element 28, the lock LI is reset to the initial zero state , in particular.

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the first trigger 10 addresses, and also goes further through the element 29 of the prohibition on the input of the gating unit 8 gating.

A pulse appears at the 24th output of block 8 and, respectively, at the 24th input of the converter 9 of the code. At the same time, pulses appear at the 2nd and 8th outputs (Fig. 3) of the converter 9, which switch the corresponding triggers 10 to one state and set the address 10000010 of the 24th memory channel address to the address inputs of the main memory unit 11. By decreasing the address pulse, a second one-shot 25 is started, the output rewrite pulse of which overwrites the previous contents of the 24th memory channel of the AND block into the binary counter 13.

After the recycle pulse decay, the one-shot 26 is triggered. The output pulse of the counting and recording of this one-shot after a certain time, determined by delay element 27, adds 20 to the content of binary counter 13, the new content of this counter is immediately recorded in the 24th channel the memory of block 11. The increase in the content unit of the 24th channel of the memory of block 1 1 was recorded with the occurrence of this error pulse of the 24th recording-reproduction drip, etc.

Thus, the cycle of memory channel error includes the sequential formation in time of three pulses - the pulse of setting the address go (diagram 4 in fig. 2) of the operational memory 11, the pulse of rewriting (diagram 6 in fig. 2) of the contents of the switched channel. pa.mti in binary counter 13 and. the account of binary counter 13 and the recording of the new contents (increased by 35. | ichenpy pa unit) of this counter in the included Kaiia. i memory of block 11 of operational memory.

At a frequency of 500 kHz of the reference signal of the block 5 for time division and motley-NIN of the block I 1 of the RAM on the 564 series microcircuits, the error pulse interval at the output of the multi-input element 6 must not be less than 2.08 ISS (the sum of the pulse durations 5 owls of three consecutive single-vibrators 24, 25 and 26).

To increase the speed of the device (for a limited number of the following subjects with a maximum frequency of pulses O1bibok at the output 50 of the element OR 6) is the connection of the output of the third single-oscillator 26 to the blocking input of the prohibition element 20. If the next output pulse of the element OR 6 has arrived before the wake-up of the previous channel 01 beep cycle, but after 55 switching of the start trigger 19 to the initial state, the trigger 19 is switched, i.e. it remembers the arrival of this pulse error 0

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ki, but its output signal arrives at the start of the first one-shot 24 only after the termination of the counting and recording pulse. Gating blocks 8 and 18 are necessary in order to eliminate the change of the address of the RAM block 11 by the output pulses of the time division block 5 or the decoder 34 until the pulse arrives at the addresses at the block input 5.

After the end of the monitoring of the total authenticity of the device 1 magnetic recording, it is necessary to promptly review the recorded number of errors of each recording / playback channel separately.

To enable the channel error viewing mode and then erase the memory channels of block 11, a toggle switch 14 is turned on, i.e. from control element 14, the binary counter 13 input is sent to the zero state, the blocking input of the prohibition element 21, the lock input of the element 20 prohibition, to the input of the interlocking of the prohibition element 29, to one of the inputs of the element I 17, to the information input of the eraser 35 and to the inverse setting input of the binary counter 33, thereby removing the lock from this counter by its installation value left state input.

Binary counter 33 is in the zero state. According to this state, a signal is present at the first output of the decoder 34, which is not used in the device.

The blocking of the prohibition element 20 prevents the device from operating in the channel error viewing mode by the output pulses of the time division block 5.

The blocking of the prohibition element 21 provides the read mode of the block 11 of the RAM.

The required memory channel number is turned on with the appropriate number of button presses 15.

The first memory channel is turned on by pressing the button 15 once, at the time of which pressing the protection trigger 36 switches, the output signal of which passes through the AND 32 element and enters the counting input of the binary counter 33, and also passes through the OR 22 element to start the one-shot 24 .

The binary counter 33 switches and a signal appears at the second output of the decoder 34, which is fed to the first input of the gating unit 18.

On the other hand, the address pulse from the output of the one-shot 24 arrives at the blocking input of the RAM block 11 and through the reset delay element 28 to the initial, zero, address trigger status 10, and also passes further through 11

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Ment 17 at the gating input of gating unit 18. After that, a pulse appears at the first input of the code converter 9 and the address code of the first memory channel is set at the outputs of the flip-flops 10. The contents of the first memory channel are then output to the outputs of the RAM 11 and are indicated by the display 12.

After the second button 15 is pressed again, the binary counter 33 is switched (i.e., the counter 33 counts the button 15 presses), as a result of which a signal is set at the third output of the decoder 34 and, therefore, at the second signal input of the gating unit 18. This also starts the one-shot 24, the output pulse of which blocks the RAM 11, resets the first address trigger 10 to the zero state and enters the gating input of the gate 18. A pulse is formed at the second input of the code converter 9, causing the output of the triggers 10 to be set to the address of the second memory channel, the contents of which are then output to the display unit 12.

The third memory channel is turned on by pressing the button 15 for the third time, etc.

The trigger 36 is intended to protect the controlled circuits from the contact bounce of the control element 15.

For greater convenience of working with the device by indicating and not remembering the memory channel number by the operator when reading its contents, for example, an additional display unit can be connected to the outputs of the decoder 34.

thirty

From the output signal of the frequency divider 30, the binary counter 33 automatically switches and, accordingly, a signal is generated alternately on all outputs of the decoder 34.

The output signal of the frequency divider 30 passes through the AND 31 element and also goes through the OR 22 element to trigger the one-shot 24, which periodically generates an address pulse at the time of each switch of the decoder 34.

As a result, the outputs of the flip-flops 10 enumerate the addresses of all the memory channels of unit 11. The zeroing of each memory channel occurs here because the operational memory unit 11 is in the recording mode and its information inputs have only zeroes at that time, because of the binary the counter 13 is in the zero state from the signal of the control element 14.

That is, erasing occurs by writing to each memory channel the zero content of the binary counter 13.

When a signal appears at the last output of the decoder 34, the erase trigger 35 is set to the initial state.

Claims (1)

Invention Formula A device for controlling a multichannel magnetic recording apparatus, comprising a generator, one output of which is connected to an input of a code generator, outputs connected to the inputs of a multichannel magnetic recording apparatus, outputs of which are connected to the inputs of a multichannel, error extractor unit, the output of which is 35 connected to the inputs of the block timediodes in an amount equal to the number of memory channels. After viewing the contents of all the memory channels of the RAM block 11, the memory channels of the block 11 should be reset. This operation in the proposed device, in contrast to the known one, is performed automatically after a single signal from the control element 16. Each time before turning on the zeroing mode of the memory channels of block 11, and also before re-enabling viewing of channel errors, it is necessary to turn off and then again switch on control element 14. This is achieved by setting the initial, zero, state of the binary counter 33. The output of control element 16 switches the erase trigger 35, the output of which opens element AND 31 for passing the output low-frequency (8 Hz) signal of frequency divider 30 to 40 It is connected to the second output of the generator, and the outputs are connected to the inputs of the gating unit and to the inputs of the OR multi-input element, the output of which is connected to the error counter and to the nepBt iM input of the trigger trigger, the output of which is connected through the serially connected first element -eta, the first element OR, the first one-shot, the second element of the prohibition, the second with a swarm of one-shot, the third one-shot, the output of which is also connected to the first input of the lock of the first element of the ban, the second element The ORT and the first delay element with the control input of the RAM and the counting input of a binary counter connected to the outputs and information inputs of the RAM, the outputs of which are connected to the group of installation inputs of the binary counter and the inputs of the display unit, and the address inputs the inputs are connected via a group of the three-digit input of the counter 33, as well as 55 characters of the address with the converter outputs however, it passes through the element OR 23, the element 27 of the delay, and places the operational memory unit 11 in the recording mode. code, the inputs of which are connected to the outputs of the gating unit, the first control element, the output connected to the second input five 0 0 From the output signal of the frequency divider 30, the binary counter 33 automatically switches and, accordingly, a signal is generated alternately on all outputs of the decoder 34. The output signal of the frequency divider 30 passes through the AND 31 element and also goes through the OR 22 element to trigger the one-shot 24, which periodically generates an address pulse at the time of each switch of the decoder 34. As a result, the outputs of the flip-flops 10 enumerate the addresses of all the memory channels of unit 11. The zeroing of each memory channel occurs here because the operational memory unit 11 is in the recording mode and its information inputs are at this time only zeros, probably binary the counter 13 is in the zero state from the signal of the control element 14. That is, erasing occurs by writing to each memory channel the zero content of the binary counter 13. When a signal appears at the last output of the decoder 34, the erase trigger 35 is set to the initial state. Invention Formula A device for controlling a multi-channel magnetic recording apparatus, comprising a generator, one output of which is connected to the input of a code generator, outputs connected to the inputs of a multi-channel magnetic recording apparatus, outputs of which are connected to the inputs of a multi-channel, error isolation block, outputs connected to the time block inputs It is connected to the second output of the generator, and the outputs are connected to the inputs of the gating unit and to the inputs of the OR multi-input element, the output of which is connected to the error counter and to the nepBt iM input of the trigger trigger, the output of which is connected through the serially connected first element -eta, the first element OR, the first one-shot, the second element of the ban, the second one-shot, the third one-shot, the output of which is also connected to the first input of the lock of the first element of the ban, the second element t OR and the first delay element with the control input of the RAM and with the counting input of a binary counter connected to the outputs and information inputs of the RAM, whose outputs are connected to the group of installation inputs of the binary counter and the inputs of the display unit, and the address inputs connected through a group of triggers whose inputs are connected to the outputs of the gating unit, the first control element, the output connected to the second input 13 blocking the first prohibition element, with the blocking input of the second prohibition element, with the first input of the And element and with the FJOBOMHbiM input of the binary counter, the control input of which is connected to the direct output of the second one-shot and the second trigger trigger input The output of the first one-shot is additionally connected to the blocking input of the RAM block and to the input of the second delay element whose output is connected to the second inputs of the address triggers, characterized in that, in order to Time control with channel analysis error, serially connected frequency divider connected to the second generator input, additional AND element, additional OR element, additional binary counter, decoder and additional gating unit, whose outputs are connected to the code converter inputs, erase trigger, first login ppils addresses FIG. 2 14 five 0 connected to the output of the third control element, the second input to the output of the first control element and the installation input of an additional binary counter, the third input to the last output of the descrambler, and the output to the second input of the additional element AND and the second input of the second element OR, additional element blocking, the output connected to the gate input of the gating unit, the blocking input to the output of the first control element, and the signal input to the output of the second delay element and to the second input the house of the AND element, the output of which is connected to the gate input of the additional gating unit, and the protection trigger, the inputs connected to the outputs of the second control element, and the output connected to the second input of the additional OR element and the second input of the first OR element, the third input of which is connected to the output of the additional OR element element I. 70 Q 000 00 About 0000 0000 0000 0000 0000 0000 0000 about TOO 0000 00 00 0000 0000 0000 0000 0000 0070 about 00 00 00 0000 0000 00 about 1 FIG. 3