SU1415452A1 - Transceiver of digital signals - Google Patents

Abstract

The invention relates to telecommunications and allows to increase noise immunity by reducing transition and intersymbol interference. The device contains on the transmitting side a carrier frequency generator 1, an information source 2, an OF element, a counting flip-flop 4, an adder 5 modulo two, adders 6, 8-10, LZ 7, 11-14, sectors 15-17 and switches 18 , 19 operating modes, and on the receiving side amplifier 20, delay element 21, adder 22, pulse shapers 23, 24, element Я1И 25, trigger 26, and a decisive block 27. A biopulse level information signal is generated on the e gear in the adder 5. The elements of the signal, containing the first harmonics of the half-clock frequency, correspond to single code symbols, and the elements of the signal containing the first harmonics of the clock frequency correspond to zero code symbols. At the output of the adder B, a linear signal is formed, in the energy spectrum of which the low-frequency component is suppressed, and the max, the energy in the spectrum is concentrated at the clock frequency. The other four modes of operation of the device, provided by switching the switches 18, 19, are characterized by the equivalent power of the single and zero symbols. 2 Il. SO with

Description

sd d ate to

The invention relates to telecommunications and can be used for high-speed transmission of digital information.

The purpose of the invention is to increase noise immunity by reducing oversampled and intersymbol interference.

FIG. .1 shows the structural electrical circuit of the proposed device; in fig. 2 - time diagram.

A device for transmitting and receiving digital signals contains on the transmitting side a carrier frequency generator 1, an information source 2, an IZ element, a counting flip-flop 4, an adder 5 modulo two, an adder 6, a delay line 7, the first, second and third additional adders 8 - 10, the first second, third and fourth additional delay lines 11-14, the first, second and third selectors 15-17, the first and second switches 18 and 19 of the operating mode, and on the receiving side the amplifier 20, the delay element 21, the adder 22, the first and second shaper 23 and 24 pulses, e OR 25; trigger 26 and decision block 27.

A device for transmitting and receiving digital information operates as follows.

According to the cycles of the carrier frequency generator 1 (Fig. 2a), the information source 2 generates a standard two-level digital signal in the serial code (Fig. 26). The modes of the transmission rate of the signal are set by the carrier frequency generator 1 depending on the band used for a particular communication channel. Modulator 2 modulo two generates a bi-pulse digital signal and simultaneously recodes the absolute code of digital information into relative, therefore, an input And 3 and a counting trigger 4 are connected to the input for pre-encoding the relative code (Figure 2c and d) . Then at the output of the adder 5 modulo two receive a digital signal (figd) which elements correspond to code symbols in absolute value, i.e. the signal elements containing the first harmonics of the half-cycle frequency correspond to single code symbols (for a half-period), and the signal elements containing the first harmonics

g

5 0 5 Q

.. five

0

clock frequency, correspond to zero code symbols (for the period).

In the adder 6, the digital bi-pulse signal (Fig. 2d) is summed with the inverse digital signal and the delay of the first delay line 7 T / 4 (clock period) (Fig. 2e). At the output of the adder 6, a digital bipolar signal is formed (Fig. 2g) with a suppressed low frequency component in the signal spectrum, which is used as a linear signal for transmitting digital information. A bipolar digital signal (Fig. 2g) is then fed to the first input of the adder 8, to the second input of which a signal (with a negative sign) is connected to elements of code zeros delayed by the second delay line 12 and allocated to the selector 15 (Fig. 2h). At the output of the adder 8, a linear signal is formed (Fig. 2i), in the energy spectrum of which the low-frequency component is suppressed, and the maximum energy in the spectrum is concentrated at the clock frequency. In such a signal, the elements of its zero symbols have the potential equivalent power (P A) and the elements of the single symbols have equivalent power (P,). Therefore, the generated linear signal has potential noise immunity for the upper extreme band of the channel, the wired link. And the transmission in the extreme upper band of the channel provides the maximum speed of transmission of digital information. Suppressing the low frequency component in the signal spectrum reduces the effect on signals that can be transmitted simultaneously in a channel band at lower frequencies.

The same signal is received in the second and third modes if the delay line 13 and the selector 16 form a signal (Fig. 2k), and the adder 9 summarizes the signals in the second, or in the third mode, switched by the operation mode switch 18.

The fourth and fifth modes, connected by the operating mode switch 19, form a digital linear signal with potential noise immunity of the half-frequency frequency elements (for elements from common symbols and zero-character elements), for example

3 1

digital information and the lower channel edge bandwidth (Fig. 2n), and a signal (Fig. 2o) with potential r at the Half-Clock and Clock Frequency (for zero and single symbols) and with partially suppressed low-frequency and high-frequency components in the spectrum, which has potential noise immunity in the central band of a frequency-limited channel,

In the fourth and fifth mode, the delay line 11 shifts the bi-pulse signal (FIG, 2L); in the shifted signal, the delay signal line 1A is shifted by signal zeros by tT T / A (FIG. 2m) towards the front, selected by the selector 17, And in the cy -1mator 10, the required linear signals are formed (Fig. 2n and o).

At reception, amplifier 20 compensates for link losses. Its constant coefficient in the passband of the information frequencies r sharply decreases in the stopband of all high-frequency components. To compensate for symbolic and low-frequency interference, delay element 21 is used, obtained according to the phase shifter (О, .- 180), Tak. The fairer is a phase filter, which allows using the sump 22 to compensate for phase distortions introduced by the nonlinearity of the frequency response of the link. After such filtering, the signal takes the form (Fig. 2p) with the signs of the clock frequency (stable zero line) and signs of information of the first characters

0 and 1 in amplitude due to the redistribution of energy into the low-frequency region due to the uneven amplitude-frequency characteristics of the channel, which are used advantageously.

Shaper 24 pulses exceeding the threshold contains a level selector circuit and an amplitude discriminator circuit on comparators (not shown), which extract pulses when the threshold level is exceeded in comparators (Fig. 2c). The signal also enters the zero level pulse generator 23, which contains the circuit the amplifier-limiter and the zero-comparator circuit (shown in y) and generates pulses when the signal passes the zero level (fig.2r).

Element Ш1И 25 summarizes the pulses arriving at its inputs from forma- tor 23 and 24, and the trigger 26 divides the frequency of the pulses (FIG. 2t) into two, restoring the clock frequency (FIG, 2u), and for stable synchronization of the decisive block 27, the trigger 26 each time it is set

in a single state on the leading edge of the pulse, the form of 24 impulses exceeds the threshold. Decision block 27 is a trigger circuit that is set to one

the state at the coincidence of the pulse frequency and the pulse of the former 24 exceeds the threshold and is reset to the zero state when the next pulse of the clock coincides

frequency (Fig, 2F),

The use of the proposed device for transmitting and receiving digital information makes it possible to use optimal digital linear signals.

for wired communication lines and the corresponding waveform spectrum, which have not previously been applied in practice,

Claims (1)

Invention Formula A device for transmitting and receiving digital signals, comprising on the transmitter side an information source, the output of which is connected to the first input of the element I, the second input of which is connected to the output of the carrier frequency generator, the counting trigger, the modulo two, the delay line and the adder, and on the receiving side -. the amplifier, the output of which is connected to the first input of the adder and to the input of the delay element, the output of which is connected to the second input of the accumulator, is 5 the stroke of which is connected to the input of the first pulse driver and to the input of the second pulse driver, the output of which is connected to the first input of the decision unit, the second input of which is connected to the output of the trigger, the first of which is connected to the output of the OR element, the first input of which is connected to the output of the first pulse generator, characterized in that, in order to increase noise immunity by reducing transient and intersymbol interference, the first, second, third and fourth additional lines are introduced on the transmitting side u z