SU1177917A1 - Device for transmission and reception of information - Google Patents

Description

The invention relates to telecommunications and can be used to transmit data over the channels of the tone frequency in systems with frequency division channels. five

The purpose of the invention is to improve the noise immunity. ,

FIG. 1 shows a block diagram of a device for transmitting and receiving information; in Fig.2 - Yu the same block allocation of clock frequencies; fig.Z - the same block allocation of frequencies.

The device for transmitting and receiving information contains a driver 1 .15

parcels, generator 2 carrier frequency, phase modulator 3, block 4 dedicated-. clock frequencies, the first band-pass filter 5, the frequency detector 6, the output unit 7, the second band-pass 20 filter 8, the phase detector 9, the filter.

10 low frequencies, a decisive block 11, a block 12 for allocating frequencies and a frequency detector 13.

The block 4 of the allocation of clock frequencies 25 contains a multiplier 14, a third band-pass filter 15, an amplitude detector 16, a threshold unit 17, a sawtooth voltage generator 18 and a controllable delay unit 19. h ₀

The frequency allocation unit 12 comprises a multiplier 20, a fourth band-pass filter 21, a synchronous detector 22, a fifth band-pass filter 23, an amplitude detector 24, a threshold unit 25, a sawtooth voltage generator 26, and a controlled delay unit 27.

The device for transmitting and receiving information works as follows

The shaper 1 on the transmitting side forms DC bursts that modulate the carrier formed by the oscillator 2 in the phase modulator 3. 45

The width of the spectrum of this signal is determined by the duration of the elementary

the symbol of the modulating sequence. Moreover, the width of the main spectrum lobe is equal to twice the clock frequency of the sequence of elementary symbols of the sequence. It determines the bandwidth of the first bandpass filter 5. With the help of block 4, the allocation of the clock frequency and frequency detector 6, the bandwidth of the first bandpass filter 5 is adjusted. This is done as follows. The generator 18 is turned on, the signal from the output of which changes the delay time of the block 19 and the tuning frequency of the third band-pass filter 15, and the delay and frequency changes occur linearly. The multiplier 14 performs the operation of multiplying the elements of the modulating sequence of detainees relative to each other. The signal at the multiplier output

14 contains a clock component. The amplitude of the component is maximal · with the delay of elements equal to half the duration of the elementary parcel. Third band filter

The 15 clock frequency is filtered through the amplitude detector 16, where the clock envelope is highlighted.

When the envelope reaches the maximum value, the threshold unit 17 is triggered, the response threshold of which depends on the amplitude of the modulating sequence. When triggered, the threshold unit 17 generates a signal stopping the generator 18, while the voltage level at the output of the generator 18 remains constant and equal to the voltage level at the moment of stopping. This fixes the value of the delay and frequency in block 19 and the third band-pass filter 15. The signal from the output of the third band-pass filter 15 is fed to the output of block 4 and then to the input frequency

3 1177917

detector 6, which generates a signal whose amplitude is proportional to the value of the clock frequency. This signal also changes the bandwidth of the first bandpass filter 5. The bandwidth 5 of the first bandpass filter pa 5 becomes equal to twice the clock frequency, as a result of which the latter passes only the main lobe of the signal spectrum, suppressing 10 all other signal components. Next, the signal enters the output unit 7, which amplifies the signal.

On the receiving side, the second half-pass filter 8 selects the spectrum of the signal transmitted to the communication channel. The bandwidth of the second band-pass filter 8 is adjusted to the width of the main lobe 20 of the signal spectrum. The adjustment of the bandwidth is carried out using block 12 and frequency detector 1 3.

The principle of operation of frequency allocation unit 10 is based on the same theoretical principles as the principle of operation of unit 4, i.e. when multiplying the signal in multiplier 20 by a signal delayed by half the duration of the 3θ _Β elementary parcel in block 27, the output of multiplier 20 produces a signal in the form of beats with high-frequency filling, the beat frequency equal to the clock frequency of the modulating sequence, the fourth band filter 21 on

high quality filling and highlight carrier frequency. The signal with the carrier frequency, as well as the signal from the output of the multiplier 20, is fed to the synchronous detector 22. The fifth band-pass filter 23 selects the clock frequency, and block 27 and the fifth band-pass filter 23 are rearranged by the signal from the output of the generator 26, which captures the output voltage during processing threshold block 25. The latter is triggered when the envelope of the clock frequency selected by the amplitude detector 24 reaches the maximum value.

Thus, block 12 selects the carrier and clock frequencies from the incoming signal.

The carrier frequency from the output of the fourth bandpass filter 21 enters the phase detector 9, with the result that the modulating sequence is fed to the filter 10. The clock frequency from the output of the fifth band-pass filter 23 is fed to the input of the decision block 11 and the frequency detector 13. The latter generates a signal whose amplitude is proportional to the clock frequency. This signal adjusts the bandwidth of the second band-pass filter 8. At the same time, the clock frequency signal gates the elementary premises in the decision block I1, which restores the shape of the elementary symbols.

1G

ί 1Ζ

7.-¼.

1

“

1177917

figs

Claims (3)

1. TRANSMISSION AND RECEPTION DEVICE OF INFORMATION, containing on the transmitting side. A parcel generator and serially connected carrier frequency generator, phase modulator, first band-pass filter and output unit, and on the receiving side - serially connected second band-pass filter, phase detector, low-pass filter and a decisive unit that differs from that in order to improve noise immunity, a serially connected clock extraction unit and a frequency detector, the output of which is unified with the control input of the first bandpass filter, the input of the clock selection block is combined with the input of the phase modulator and connected to the output of the parcel generator, and on the receiving side are introduced a series-connected frequency allocation block and a frequency detector, the output of which is connected by a controlled input of the second band filter The input of which is combined with the input of the frequency allocation unit, the first output of which is connected to the second input of the decision unit, and the second output of the frequency allocation unit is with the second input of the phase detector. 2. Device by π. 1, characterized in that the clock extraction unit contains a serially connected multiplier, a third band-pass filter, an amplitude detector, a threshold unit, a sawtooth generator and a controllable delay unit, the information input of which is connected to the first input of the multiplier and is the second the multiplier input is connected to the output of the controlled delay block, whose control input is combined with the control input of the third band-. filter, whose output is the output of the block allocation of clock frequencies. 3. The device according to claim 1, characterized in that the frequency allocation unit contains a series-connected multiplier, a fourth band-pass filter, a synchronous detector, a fifth band-pass filter, an amplitude detector, a threshold block, a sawtooth voltage generator and a controlled delay block, the information input of which is combined with the first input of the multiplier, which is the input of the frequency allocation block, the second input of the multiplier is connected to the output of the controlled delay block, the control input of which is combined with the control input of the fifth bandpass filter, the output of which ЗЦ 1177917 1177917 is the first output of the frequency allocation unit, the second output of the synchronous detector is combined with the input of the fourth bandpass filter, the output of which is the second output of the frequency allocation unit.