SU1462509A1 - Receiver of digital linear signal - Google Patents

Abstract

The invention relates to telecommunications. The circuit of the invention is an increase in noise immunity. The receiver contains an amplifier 1 with automatic gain control (AGC), a signal equalizer 2, a level selector 3, an amplitude discriminator 4, a decisive block 5, a threshold driver 6, an adder 7 rib module two, a driver 8 short pulses, trigger 9, delay line 10, low pass filter 11 and integrator 12. The input signal through amplifier 1, which suppresses high-frequency interference, is fed to equalizer 2. When the signal level at output of equalizer 2 changes, adder 7 generates a signal that is different from the reference square wave. At the same time, at the output of the integrator 12, a signal with a constant component, which is received by the filter 11, appears and is transmitted to the AGC input of the amplifier 1 as a control signal. The AGC control signal changes the coefficient. amplifying amplifier 1 in the direction of decreasing the error signal. T.V. The receiver makes it possible to increase the noise immunity of receiving digital information for various types of fluctuation changes in the parameters of the communication channel. 2 Il. e w

Description

 FIG. one

The invention relates to telecommunications and can be used in data transmission systems.

The purpose of the invention is to increase the resistance to wear.

FIG. 1 shows the structural electrical circuit of the proposed receiver; in fig. 2 - time diagram of work, receiver. i The receiver of a digital linear signal contains an amplifier 1 with automatic gain control (AGC), I corrector 2 signals, a selector 3 levels 10

frequency (signal of single code symbols) from signals at higher frequencies (zero code symbols (Fig. 2d), and amplitude discriminator 4 generates impulses to exceed the level set in it (Fig. 2e), which are input to the decisive Block 5 The signal from the output of the equalizer 2 also arrives at the input of the threshold generator 6, which contains an amplification circuit with amplitude limiting and a zero-comparator circuit.

n, amplitude discriminator 4, re-15 output of the threshold driver 6

block 5, threshold shaping unit: body 6, adder 7 modulo 2, form- | Worlds 8 short pulses, Trigger 9, delay element 10, | low-pass filter (LPF) and in: tegrator 12. At the same time, corrector the signal contains a differentiator 13, a phase filter 13 and an adder 15. The receiver works as follows.

; Amplifier 1 matching, according to. A bath with a specific line compensates for the energy loss in the line. Its gain is linear in the band, information frequencies, and has a sharp decrease in the stop band, which provides for the suppression of high frequency interference. The signal is then fed to the input of the corrector 2, in which this input is connected to the input of the trimmer 13. The latter provides: Linear filtering of the signaling, i.e. ; increases the level of the information signal at the clock frequency with respect to the low-frequency interference.

The output signal of the differentiator 1P is fed to the input of the phase filter 14, adjusting the passive parameters (RC) of the circuit; form the phase characteristic of the phase filter 14 such that at the output of the adder 15 a signal is received (FIG. 26.) with a stable zero line and with fixed envelope parameters of the first harmonics for the corresponding code symbols. For this, the second input in the antiphase receives a signal from the output of the differentiator 13, and the third input of the adder 15 is connected to the signal from the output of the amplifier 1.

The corrected signal from the output of corrector 2 is fed to the input of the level selector 3, in which the signal of the semi-clock is selected

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(Fig. 2c) is connected to the first input of the adder 7 modulo 2 and to the second input of the trigger 9, the signal from the output of the 10 delay element 10 (Fig. 2e) is connected to the first input.

The delay element 10 delays the leading edge of the pulse by a standard duration (tj) so that the trigger 9 switches at the moment (Fig. 2g) of the extremum of the signal Corresponding to a single code symbol. Then, at the output of the modulo 2 adder, a pulse wave signal is generated (Fig. 2h).

The pulse shaper 8 for the front of pulses overloads short pulses (Fig. 2k), which are fed to the clock input of the decision block 5, the output of which encodes 1 or C symbols (Fig. 2n) are fixed. 2 is also fed to the input of the integrator 12 and then through the low-pass filter to the AGC input of amplifier 1.

A signal arriving at the AGC input of amplifier 1 is generated as follows.

At a constant signal level at the output of the signal equalizer 2 and at the output of the adder 7 modulo two, a signal is formed (Fig. 2h, solid line) of the Meander type, in which there is no constant component. At the output of the integrator 12, a signal is generated (Fig. 2i, a line) with a constant component, which is fed to the input of the LPF 11, at the output to which in this case there is no control signal at the AGC input.

When the signal level changes in the code of the corrector 2 signal at the output of the adder 7 modulo 2, a signal is generated (Fig. 2h, dashed line).

frequency (signal of single code symbols) from signals at higher frequencies (zero code symbols (Fig. 2d), and amplitude discriminator 4 generates impulses to exceed the threshold level set in it (Fig. 2e), which are fed to the decision block 5. The signal from the output of the corrector 2 is also fed to the input of the threshold shaper 6, which contains an amplification circuit with amplitude limitation and a zero-comparator circuit.

output threshold shaper 6

5 output threshold shaper 6

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(Fig. 2c) is connected to the first input of the adder 7 modulo 2 and to the second input of the trigger 9, to the first input of which the signal from the output of the delay element 10 is connected (Fig. 2e).

The delay element 10 delays the leading edge of the pulse by a reference duration (tj) so that the trigger 9 switches at the time (Fig. 2g) of the extremum of the signal Corresponding to a single code symbol. Then, at the output of the adder 7 modulo 2, a pulse signal Meander is formed (Fig. 2h).

The shaper 8 pulses on the falling edge of the pulses accumulates short pulses (Fig. 2k), which arrive at the clock input of the decisive. block 5, the output of which is fixed code symbols 1 or C (Fig. 2L), the signal from the output of the adder 7 modulo 2 is also fed to the input of the integrator 12 and then through the low-pass filter to the AGC input of amplifier 1.

A signal arriving at the AGC input of amplifier 1 is generated as follows.

With a constant signal level at the output of the corrector 2 signal and at the output of the adder 7 modulo two, a signal is formed (Fig. 2h, solid line) of the Meander type, in which there is no constant component. At the output of the integrator 12, a signal is generated (Fig. 2i, a line) without a constant component, which is fed to the input of the LPF 11, the output of which in this case is not affected by the control signal at the AGC input.

When the signal level changes in the code of the corrector 2 signal at the output of the adder 7 modulo 2, a signal is generated (Fig. 2h, dashed line).

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different from the reference meander. At the same time, a signal appears at the output of the integrator 12 (Fig. 2i, dashed line) with a constant component, which is detected by the low-pass filter 11 and transmitted to the AGC input of amplifier 1 as a control signal. The AGC control signal changes the gain of amplifier 1 to the side of reducing the error signal (control effect for AGC).

Thus, the proposed digital linear signal receiver can improve the noise immunity 15 of receiving digital information with various kinds of fluctuating changes in communication channel parameters.

Claims (1)

Invention Formula A digital linear signal receiver containing a corrector, the output of which is connected to the input of the level selector and 25 to the input of the threshold shaper. 1462509 Yu 15 20 25 the output of which is connected to the first input of the modulo-two adder and the first input of a trigger, the output of which is connected to the second input of the modulo-two adder, the output of which is connected to the first input of the decision unit, the second input of which is connected to the output of the amplitude discriminator, the input of which is connected to the output of a level selector, characterized in that, in order to increase noise immunity, a delay line, an integrator, a low-pass filter and an amplifier with automatic gain control are introduced audio, automatic gain control input of which is connected to the output of the lowpass filter, whose input is -Connect to the output of the integrator, the input of which is connected to the output of the adder of modulo two, the yield of arg shlitud- Nogo through the delay line discriminator is connected to the second input of the flip-flop. four. --...: J ZX .. ./. .A l 0 / A7 H / V / . .A l H / V /