SU1411838A2 - Read-only memory checking device - Google Patents

Abstract

The invention relates to a computing technique and can be used to control blocks of permanent memory (ROM) and cable harness. The aim of the invention is to increase the reliability of the control. Device

Description

(L

with

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L contains a switching element block 1, a control block 2 consisting of a multivibrator 3, a divider 4 frequencies, a generator of 5 clock pulses of the distributor 6 clock pulses LOB, the device also contains a block of | 7 input control signals, for example, punched cards, address register 8, the second 9 and the first 17 comparison units, () 0rmi tel 10 address signals, (control unit 11, control unit 12 AND-OR elements, counter 13, decoder 14, switch 15, () lok 16 contact control code harness shaper 18 information signals, delays lement

9, a block of 20 inductive sensors, such as an inductor on pin cores, the primary winding of each of which is a wire 1 |: one harness, a current generator 21.

The invention relates to a computational technique and can be used to control constants of uninterrupted power units (ROMs) and cords, and is a refinement of the invention according to IIBT.CB, IS 1191944.

i The purpose of the invention is to increase the dignity of the control. FIG. 1 shows the ifiaK functional scheme of the proposed device Ya figure. 2 - functional diagram of the block jca analysis of the completeness of the control; in fig. 3 is a functional diagram of the most preferred .jiee variant of the above-: | 1eni distributor of clock pulses ||; s of the control unit.

The device contains (Fig. 1) a switching unit It, switching unit 2; | 1eni, consisting of a multivibrator:, a divider 4 frequencies, a driver 5 clock pulses and a distributing; | 1 я 6 clock pulses.

The device also contains a block of 7 control signals, an address register $, a second block of comparison 9, a driver of 10 address signals, a driver of control signals 11; liOB, a block of 12 AND-OR elements, a counter

an error registration block 22, an address memory block 23, a control completeness analysis block 24, a counter 25 of the number of unresolved memory cells and a block 26 of AND elements. The reliability of the control is achieved due to the fact that a block is written to block 23 when the monitored block is addressed the memory at the address set at the output of the counter 13, and zero if the control object is not monitored at this address, the end of the control is polled by block 23 Addresses that have zeros in block 23 are recorded by block 22, and the number they are fixed tchi1som 25, a control end signal is outputted analysis unit 24 monitoring the completeness only in case the recording unit block information in all cells of the memory 23, zp 1, f-ly, 3 ILA

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13, the decoder 14, the switch 15, the control harness contact block 16, the first 17 comparison block, the information signal generator 18, the delay element 19, the block

20 inductive sensors generator

21, an error recording block 22, an address memory block 23, a control completeness analysis block 24, a. 25 counter of the number of unresolved memory cells and a block of AND elements 26,

The completeness analysis analysis unit 24 contains (FIG. 2) first to fifth elements AND 27-31, the first 32 and second 33 NOT elements, the first to the third triggers 34-36, the first 37 and the second 38 delay elements, the first 39 and the second 40 elements OR, the First 41 and the second 42 start inputs, the first 43 and second 44 unlock inputs, synchronization input 45, information input 46 and the first to fourth 47-50 outputs of the completeness control analysis unit 24.

The clock distributor 6 contains (FIG. 3) elements AND 51-55, inputs 56 of element 55, elements and 58. triggers 59-62, element OR 63, delay element 64, matching elements 65-67, outputs 68-72 to the inputs 73-78 6 clock pulse distributor. 1, informational inputs 79 and outputs 80 of the device are also indicated.

The control signal input unit 7 can be executed, for example, from the UPC-M1, which allows the control information to be read from the punched card. As the unit 22 for recording errors can be applied, for example, M11U16-3 (small printing device).

The inductive sensor unit 20 may be made, for example, in the form of inductors, which are secondary windings on the pin cores, the primary winding of which is the wire of the tested cable harness.

The information signal shaper 18 is made of amplifiers, the number of which is equal to the width of the monitored code harness connected by inputs to the secondary windings of inductive-guage sensors, which generate pulse signals based on the flow of the pulse current in the e-30 wire. And .52

my code harness.

The device works as follows.

The device provides verification of functionally complete blocks of the constant memory and passive nodes of the memory - code harness,

In the first case, the monitored blocks are connected to the inputs 79 and the outlets 80 of the device, and when checking the code harnesses, the latter are placed on the core of the block 20 (FIG. 1).

The verification is carried out by comparing in block 9 numbers in binary code that are read from the control object, with control codes, the carriers of which can be a punch card or a reference memory block.

When checking a control object by reference unit, the latter is connected to inputs 79 and outputs 80 in the same way as a monitored block.

The timing diagram of the operation of the reference and controlled blocks is constructed by the shaper 11 based on the clock pulses T1 - T4, shifted one relative to the other by the duration of one clock pulse generated by the shaper 5

Pn control ROM on the reference unit, the device operates as follows. The starting pulse from the fifth output of the unit 1 to the input 73 in the distributor 6 (Fig. 3) turns on the trigger 59. On the fifth input of the driver 11 a timing control is included.

At the end of the cycle, a signal is generated, which from the output of block 11 is fed to input 76, turns on trigger 62, and the pulse T1 interrogates the elements AND 54 and 55. If the codes are equal in block 9, a single signal is generated, if not, the zero signal is generated NOT 33 is fed to the input element I55. A single signal in tact T1 generates a pulse at the output of the element And 54, and zero - at the output of the element And 55,

The pulse from the output of the element AND 54 through the element OR 63 activates the trigger 61 to enable the formation of a counting pulse for the counter 13 according to the cycle T2 by the element And 53, wherein the code. the addresses in counter 13 are incremented by one and selects the next controlled cell ROM (not shown),

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an impulse is formed, which is fed to the third input of the imaging unit 11, generates signals of the timing diagram and starts the next, control cycle.

The number of control cycles is set from block 1 by sending to the register 8 a code that corresponds to the address of the last controlled ROM cell, 0. When the end address is reached, block 17 generates a signal that, with its output, goes to input 77; : limiter 6 and prohibits formation. Signals at the output of the I.52 element to start the next cycle, - If the codes in block 9 do not match, the inequality signal takes the beat T1 by the element And 55 by the And 55 pulse of the print call, which, from output 68, goes to the input of block 22, the address is fixed malfunction and at the end of the printing operation a pulse is formed, which is fed to the input 75 of the distributor 6, the trigger 61 is turned on, the start pulse of the timing diagram of the next cycle and the count pulse at the output 69 are generated at the output 70.

The code harness is checked in the same way as a ROM check.

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51411838

Start each wire harness under 20 p

connects to the output of the deifrarator 14 through the contacts of the switch 15. The second contacts of each group through the second output of the switch 15 are connected to the input of the block 16,

With reliable contact, the signal coming from the decoder 14 passes through the controlled wire and through the second contacts enters the input of the unit 16, and from its output to the input of the forms, body 11 to activate the new control cycle. The code harness polling signal is generated by the decoder 14 according to a strobe pulse, which is supplied from the third output of the driver 11.

After interrogating the code harness in the secondary winding of inductive sensors of block 20, signals are generated that enter the driver 18. As these signals are oscillatory in nature, they are gated with a delayed interrogation signal through delay element 19 After forming, the information signals arrive at block 9, where compared to tell-tales

Block 16 pb allows you to distinguish between zero information, sewn in a cable harness, from zero information obtained in the absence of contact with the wire harness in the switch 14.

When monitoring a ROM and code harnesses according to the control information read by block 7 from punched cards, the device is controlled by signals which are formed on the basis of marker punches on punched cards. The cycle enable signals come from the second output of the block 7 to the second input of the racer 11. At the same time, the third output 70 of the distributor 6 is closed by the trigger 59, which is reset by the marker signal received at the input 74.

During the control of the ROM or code harness unit 23 operates in recording mode.

In each cell of the unit 23 at the selected address, information of a single level is recorded by a signal on the control inputs from the output 72 of the distributor 6..

Thus, by the end of the control, in unit 23, units are recorded in all cells that are selected, set in counter 13, and in which

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ki, whose address is missing at the output of counter 13j, is written down to zero information corresponding to unchecked addresses in the control object. The signal of the final address of the control from the output of block 17, which enters input 78 (FIG. 3), permits the formation of a control enable signal, which arrives at the input 42 of block 24 (fig 2), according to the tact of the TOR element and triggers 35 and 36 and so T1 From the output of the element IZ9, elements 30 and 31 are polled, the inputs of which are controlled by information on the input 47, read from block 23. If a single signal is present at the input 47, the element And 31j is triggered and the trigger 34 is turned on and the tact of TK is formed by the impulse that arrives at the counting in od counter 13 for the next test cell 23. The output address block 50 AND gate 27 has an open collector, which makes it possible to connect it to the mounting Hilti parallel output 69 of the distributor 6.

If zero information is present at information input 47 of block 24, then AND 30 is turned on and a print control signal is generated at its output 48. The output 48 of the element And 30 is integrated along the mounting OR with the output 68 of the distributor 6. The pulses from the output 48 through the delay element 37 sets the trigger 35 to the zero position, prohibiting the operation of block 24, and enables printing of the block 22L. After printing the address from the output of block 22 at input 42, turns on trigger 34 through element OR 39 and generates a counting pulse for counter 13 at output 50. The control address is increased by one and the next cycle of the device is performed.

The search for unasked cells is carried out to the final control address, at which the element 28 forms a signal, which arrives at block 1 and includes an indication signal of the end of the control. If during the control process there are unchecked addresses, then a signal is generated at the output 47 of block 24, which is fed to the counting input of the counter 25.

By the end of the control, the number of unasked 4s is recorded in counter 25

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7.1411838

ek controlled memory. The block of elements And 26 monitors the states of the outputs of the counter 25 on single levels. If there is information in the counter 25 other than zero, the block of elements And 26 on the output is closed and the indication signal of the end of the control is not formed, and the addresses of the unchecked cells of the control object register with block 22, j

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Claims (1)

Invention Formula you are the delay, the first and second elements (r or you, and the output of the first element OR is connected to the installation input to 1 of the first trigger, the output of which is connected to the first inputs of the first and second elements AND, the output of the first element AND is connected to the first input of the second element OR, the output of which is connected to the installation input to the 1st second trigger, the output of which is connected to the first input of the third element AND, the output of which is connected to the first inputs of the fourth and fifth 1. The device for controlling the CURRENT N5 elements And the output of the second element And connected to the input of the first delay element, the output of which is connected to the reset input of the third trigger, the output of which is connected to the second input 20 of the third element AND, the second input of the first element AND is connected to the output of the first element NOT, the output of the second element is NOT connected to the second input the fourth element And the output 25 which is connected to the input of the second delay element, the output of which is connected to the input of the installation in O of the second trigger, the first input. First. element OR is connected to the output memory by author, no. 1191944, which was due to the fact that, in order to increase the accuracy of the control, the device has an address memory block, an AND block, a counter of the number of unprobered memory cells, and the information input and the first output of which are connected respectively to the output of the address memory block and to the counting input of the counter of the number of unspammed memory cells, the outputs of which are connected to the inputs of the I block, the output of which is connected to the first unlock input of the analysis block of the full 30th elementwhose second input and the input of the second element are NOT-interconnected and are the information input of the block, the second input of the second element AND is the first input of the unblocking of the block, the third inputs from the first to the third AND elements and the input of the O to the first flip-flop are combined synchronization of the block, the input of the first element NOT and the fourth input of the second element AND are combined and are the second input of the block unlocking, the input of the installation to 1 and the second input of the second element OR are combined and are the first input of the start of the block, the second in Odom start of which is the second input of the first OR gate, the output of the second delay member and the output fourth AND gate are respectively The control, the synchronization input and the first start input of which are connected respectively to the fourth and sixth outputs of the control unit, the second input and output of the error recording block are connected respectively to the second output and to the second start input of the control completeness analysis unit, the third and fourth outputs of which are connected respectively to the input of the switching element block and with the counting input of the counter, the outputs of which are connected to the address inputs of the address memory block whose recording input is connected to the fifth output of the control unit, Ora unlock control input fullness analysis unit is connected to the output of the first comparator unit 2, apparatus according For 1 liter and about 35 m 40 45 that the block is analyzed by the first and second outputs of the block, the output 50 for the completeness of the control, it contains the first to the third triggers, the first to the fifth elements AND, the first and second elements NOT, the first and second elements ten CH5 thirty 35 thirty 40 thirty 45  first and second block outputs, output 50 the second element of AND is the third output of the block; the fourth exit of the Pory is the output of the first element I.i Otv FIG. 2 Oail OmrS. OtP