SU1406805A1 - Multichannel digital communication system - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the capacity of the system. The communication system includes the transmitting unit 1, the receiving unit 2, the monitoring unit 3 and the polling unit 4. The communication system operates in two modes: in the slot switching mode for transmitting discrete information and in the slot switching mode for voice transmissions. The goal is achieved by the introduction of a monitoring unit 3 and a polling unit 4, through which time slots that are not involved in speech are used to transmit discrete information. The communication system of claims 2-10 is characterized by the execution of all blocks and their nodes. They are given il. 9 hp f-ly, 10 ill.

Description

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The invention relates to radio engineering and communication and can be used in communications with pulse-code modulation.

The purpose of the invention is to increase the capacity of the system.

Figure 1 shows the structural electrical circuit of a multi-channel digital communication system; Fig. 2 is a structural electrical circuit of the transmitting unit; FIG. 3 is a structural electrical circuit of the receiving unit; 4 is a structural electrical circuit of the control unit; FIG. 3 shows a structural electrical circuit of the polling unit; Fig. 6 is a structural electrical circuit of the first key of the receiving unit; in fig. 7 is a structural electrical circuit of the second key of the receiving unit; Fig. 8 is a structural electrical circuit for determining a control unit; Fig. 9 is a structural electrical analyzer circuit of a control unit; in fig. 10 - structural electric circuit of the control unit switch.

Multichannel digital system. Communication contains the transmitting unit 1, the receiving unit 2, the control unit 3 and the polling unit 4.

Transmitting unit 1 includes .N matching transmission units 5, N transmitters 6, encoder 7, shaper 8 line signals, transfer code converter 9, discrete information transfer unit 10, transfer generator 11, shaper 12 synchronizer and first to fourth elements OR 13-16.

Receiving unit 2 consists of N matching receiving blocks 17, N receivers 18, distribution block 19, receiving generator 20, receiver send 21, decoder 22, receiving code converter 23, discrete information receiving block 24, first 25 and second 26 keys and first 27 and second 28 elements OR

Control unit 3 contains N decision blocks 29, determinant 30, analyzer 31 and the first 32 and second 33 switches.

Block 4 of the survey includes the first 34 to the second 35 decoders and the first 36 and second 37 counters.

The first key 25 of the receiving unit 2 contains the element OR 38 and N elements And 39. The second key 26 of the receiving unit

2 form the element AND 40, the element NOT 41 and the element OR 42.

The determiner 30 of block 3 contains the first to fourth elements I 43 - 46, the first to the fourth triggers 47-50, the delay line 51, the fifth element I 52 and the fifth trigger 53. The analyzer 31 of block 3 consists of the first decoder 54, the first 55 and the second 56 flip-flops, the second decoder 57, the compare block 58 and the key 59.

The first 32 and second 33 switches of block 3 contain the first element AND 60, the first trigger 61, the second element AND 62, the first counter 63, the first decoder 64, the element OR 65, the second trigger 66, the third element AND 67, the second counter 68 and the second decoder 69

A multichannel digital communication system operates as follows.

The mode of switching channels for the transmission of discrete information.

When signals come in from the subscriber’s side to the first and second inputs of matching transmission unit 5 of transmitting unit 1, these signals are transmitted via the first and second outputs of block 5 through the first 13 and second 14 elements OR, driver 8 and converter 9 to the linear-digital path, the third and fourth outputs of the transmitting unit 1, the first and second inputs of unit 3 to the first inputs of the first 43 and second 44 elements AND, the determinant 30 and the decision block a 29. To the second inputs of the first 43 and second 44 elements I receive a polling signal from the output the decoder 34 of block 4 through its first output, the seventh input of block 3, the fifth input of the decision block 29 and the fifth input of the determinant 30. The signals from the outputs of the first 43 and second 44 elements And set the first 47 and second 48 triggers of the determinant 30 to the state pick on the gear.

When signals are received from the linear-digital path in the service time slots, these signals pass through the fourth input of the system, the first input of the receiving unit 2 to the converter 23 and then through the decoder 22, the And 40 element of the second key 26 to the first input of the distribution unit 19. With the second and third outputs of the block 19 signals end

are received through the receiving matching unit 17 towards the subscriber, and through the fifth and sixth outputs of unit 2, the fourth and fifth inputs of the control unit 3 to the first inputs of the third 45 and fourth 46 elements And the determinant 30 of the decision unit 29. To the second inputs of the third 45 and the fourth 46 elements And a polling signal comes from the output of the second decoder 35 of the polling unit 4 through its second code, the eighth input of the control unit 3, the sixth input of the decision block 29 and the sixth input of the determinant 30. The signals from the outputs of the third 45 and fourth 46 elements set the third 49 and the fourth 50 triggers are on the receive state.

After installing the first to fourth triggers 47-50, the combination is established at the inputs of the first decoder 54 of the analyzer 31 of the control unit 3, indicating the freedom of the first channel 25 throws the first trigger 61 into a one-interval. Tracking number ka-. condition. Open the second

the first interval is carried out by the first 36 and second 37 counters of the polling unit 4, which operate under the influence of a clock sequence from the second outputs, respectively, of the generator 11 of the transmitting unit 1 (through its second output and the first input of the polling unit 4) and the generator 20 of the receiving unit 2 (through its the eighth exit and the second input of the polling block 4). As a result of the impact on the signal analyzer 31, the first decoder 54 of the analyzer 31 alternately sets signals 1 at its first and second outputs. These signals transfer the first 55 and second 56 triggers to a single state, and using the second decoder 57, block 58 and key 59, the output of the analyzer 31 sets up a signal allowing the selection of the first channel intervals for transmitting discrete information.

To bring the determiner 30 to the initial state of control of the service signals, a reset circuit was inserted into the O triggers 47-50 from first to fourth, including line 51, the fifth element And 52 and the fifth trigger 53. At the seventh input of the determinant 30 (the first input of the fifth flip-flop 53) receives the transmission clock of the corresponding channel interval

from the sixth output of the generator 11, and on the eighth input of the determinant 30 (the second input of the fifth element And 52)

receive clock

channel interval from the fourth output of the generator 20. The need for a reset circuit is caused by the offset relative to each other clock pulses in the transmission and reception.

The enable signal from the analyzer output 31 is fed to the first inputs of the first transfer switch 32 and the second receive switch 33, to

the second inputs of which receive the clock pulses of the channel interval, respectively, the transmission and reception, and the third inputs receive common channel pulses, respectively, transmission

and receiving (from the second outputs of the generators 11 and 20). The channel interval pulse passes through the open enable signal from the analyzer 31, the first element I 60 and the re-element I 62, and through it from the third input of the first (second) switch 32 (33), channel-wide clock pulses come to the input of the first counter 63. The number of count cycles to of the pulse occurrence at the first output of the first decoder 64 may be different in the first 32 and second

33 switches, this is due to the propagation of signals along the path. The signals from the outputs of the first decoder 64 alternately through the element OR 65 throw the second trigger 66 in

a single state, which opens the third element I 67, and through it, the channel common pulses are fed to the input of the second counter 68 and to the output of the first switch 32.

The second counter 68, having counted to a predetermined number (for example, with reference to PCM-30 - up to 8), passes through the second decoder 69 a reset pulse to O of the second trigger 66. The first counter

63 cycles, counting to the end, impart a reset pulse to the O of the first trigger 61. If in the following cycles the service signals of the corresponding channel interval do not change, then

the process is repeated until the arrival of the corresponding call signal.

The signals from the output of the first switch 32 are received through the third element OR 15 of the transmitting unit 1 to the third input of the inhibitor of the encoder 7 and prohibit coding at these times. At the same time, the same signals are received through the fourth element OR 16 of the transmitting unit 1 to the unit 10 for resolution, Reading information from its output to the fifth input of the imaging unit 8.

The signals from the output of the second switch 33 are fed through the first element OR 27 of the receiving unit 2 to block 24 to enable recording of discrete information from the path and to the third input of decoder 22 to prohibit decoding of discrete information. At the same time, the signals from the output of the second switch 33 arrive at the first input of the first key 25, allowing the passage of discrete information through the corresponding element AND 39, the element OR 38 of the first key 25 and the element OR 28 of the receiving unit 2 into the block 24, and the first input of the second key 26, prohibited by using the elements OR 42 and NOT 41 passing through the element 40 of the second key 26 of discrete information in block 19,

The switching mode of the channel interval. For the transmission of speech signals.

When a hold signal arrives at a conversation, for example, the first channel interval at the input of the first decoder 54 of the analyzer 31, an appropriate occupancy pattern appears, which at its third output generates a reset signal in the first 55 and second 56 triggers. As a result, the enabling signal at the output of the analyzer 31 disappears, the first 32 and second 33 switches of block 3 do not work. Transmitting 1 and superb 2 blocks work, so: the voice signal is transmitted sequentially in the corresponding transmitter 6, encoder 7, driver 8 and converter 9; at the reception, the speech signals are sequentially processed in the converter 23, the decoder 22 and distributed by block 19 to the corresponding receiver, 18.

The shaper 12 and the receiver 21 synchronizing provide synchronous operation of the blocks of the system.

TaKiiM way, time intervals not involved in speech, using6

for transmission of discrete information

Claims (5)

Invention Formula 1, A multi-channel digital communication system comprising a transmission unit, the N first inputs of which are the first service information inputs N second inputs - the second service information inputs, N third inputs - analog inputs, the fourth input - the multi-channel digital data input communication systems, the channel output of which is the first BE-1 of the transmitting unit, the receiving unit whose N first outputs are the first overhead information, N second outputs - the second outputs of the service information, N third outputs - analog outputs, the fourth output - the data output of the multichannel digital communication system, the second channel the input of which is the first input of the receiving unit, characterized in that, in order to increase the capacity of the system, it is additionally introduced connected to the polling unit and the control unit, the first and second synchronization inputs of which are connected to the first and second inputs of the polling unit, respectively, the second output of the transmitting unit and the eighth output of the receiving unit, to the N second inputs of which are connected the N control output outputs of the control unit, to N the first and N second inputs of the analysis of the reception mode of which are connected to the N fifth and N sixth outputs of the receiving one. unit, the N seventh outputs of which are connected to the N second clock inputs of the control unit, the first N clock inputs of which are connected to the N second outputs of the transmitting unit ,. The N fourth and N attempts of the outputs of which are connected to the N first and N second inputs of the analysis of the transmission mode of the control unit, the N outputs of the transmission mode control are connected to the N data inputs of the transmitting unit. 2. The system according to claim 1, wherein the transmitting unit comprises N matching transmission units, the N first, N second and N third inputs of which are the first, second and third inputs of the transmitting unit, the first outputs of each of the N 714 matching transmission blocks are connected to the N inputs of the first OR element and are the N fourth outputs of the transmitting unit, the second outputs are to the N inputs of the second 9 CRI element and are N p head outputs of the transmitting unit, the third outputs are to the first inputs of each of the N transmitters, outputs which, via serially connected encoder and linear signal shaper, to the second and third inputs of which are connected the outputs of the first and second OR elements, are connected to the input of the transfer code converter, the output of which is the first output pM transmitting unit, and a second and third inputs respectively connected to the output of the encoder third its element OR and the first output of the generator - 20 receiving unit, and to the first input Transmitter, the second output of which is the second output of the transmitting unit, the third output through the fourth connected OR element and the discrete information transmission block, the first output of which is connected to the first input of the third OR element, N second inputs of which and N second inputs of the fourth OR element The data inputs of the transmitting unit are connected to the fourth input of the linear wave shaper, to the fifth input of which the output of the synchro parser is connected, to the input of which four The third output of the transmission generator, whose N fifth and N sixth outputs are respectively connected to the fourth inputs of each of the N matching transmission blocks and to the second inputs of each of the N transmitters, and the second input of the discrete information transmission block is the fourth input of the transmitting block. 3. The system according to claim 1, 1 and 2, so that the receiving unit contains N receivers connected in series, the inputs of which are connected, the first N outputs of the distribution unit, and N matching receiving units, N first, N second and N third outputs of which are respectively the first, second and third outputs of the receiving unit, the N fifth and N sixth outputs of which are the second and third outputs of the distribution unit, the first input of which is connected to the output of the second key, respectively the second input is the output of the receiver sync sending through the receiving generator whose second output is the eighth output of the receiving unit, the N seventh outputs of which are the N third outputs of the receiving generators connected to the fourth inputs of each of the N matching receiving blocks, the fourth output of the distribution unit through the second OR element to the second the input of which is connected to the output of the first key, is connected to the first input of the receiving unit of discrete information, the first output of which is connected to the first input of the first OR element, the output of which is connected to the second receiving at the input of the digital information, the second output of which is fourth output decoder, to the second and third inputs of which are connected the fourth output of the receiving generator and the output of the receiving code converter, connected to the second input of the receiving generator and the receiver input of the synchro send, and the output of the decoder is connected to the first input, - the first and second keys, N second whose inputs are connected to the N second inputs of the first OR elements and are the N second inputs of the receiving unit, the first input of which is the input of the receive code converter, 4. Pop-up system 1, characterized in that the control unit consists of N decision blocks, each of which contains a serially connected determinant whose first input is the first input of the transfer mode analysis, the second input is the second input of the transfer mode analysis, the third and the fourth inputs are the first and second inputs of the reception mode analysis, the fifth and sixth inputs are the signal selection inputs, the seventh and eighth inputs are the first and second clock inputs of the control unit, and the analyzer whose output is connected to the first inputs of the first and second ereklyuchateley, second inputs of which are connected to the seventh and eighth inputs determinator, third inputs of first and second switches are a ninth and a tenth input unit and decisive. the first and second synchronization inputs of the control unit, and the outputs of the switch - the first and second outputs of the decision unit. 5. Pop-up system 1, characterized in that the interrogation unit comprises a first counter connected in series, the input of which is with the first input of the interrogation unit, and a first decoder, the N outputs of which are the N first inputs of the interrogation unit, and series-connected the second counter, whose input is 10 of which are the second inputs of the fifth with the second input of the polling unit, and the second flip-flop and the fifth element I. A swarm decoder, the N outputs of which are the N second outputs of the polling unit. 6, The system according to claim 3, which is different from the fact that the first key of the receiving unit contains N elements AND whose first inputs are the first input of the key, the second inputs are N second inputs of the key, the outputs of the N elements AND are connected to N the inputs of the OR element, the output of which is the key output, 7. The system according to Clause 3, characterized in that the second key of the receiving unit contains serially connected element OR, whose N outputs are N second inputs of the second key, the element NOT and the element 9. The system according to claim 4, characterized in that the analyzer of the control unit contains the first decoder, 15, the first, second, third and fourth. "The inputs of which are respectively the first, second, third and fourth inputs of the analyzer, the first output of the first decoder through the first A trigger 20 is connected to the first inputs of the second decoder and comparator unit, the outputs of which are connected to the first and second inputs, the key whose output. It is the output of the analyzer25 pa, the second output of the first decoder is connected to the first input of the second trigger, the third output to the second inputs of the first and second triggers, the output of the second trigger is connected to And, the second input of which is the first to the second inputs of the second decoder and the second input is the second key, and the output is the comparison block. the first output of the second key. The system of claim 4, is different. The system of claim 4, characterized in that the switch the control unit contains sequentially connected first elements AND whose inputs are the first and second so that the determinant of the control unit contains the first, second, third, fourth AND elements whose first inputs are the first, second, third and fourth inputs the determinant, the second inputs of the first and second elements And are the fifth input of the determinant, the second inputs of the third and fourth elements And the sixth input of the determinant, the outputs of the first, second, third and fourth elements And connected to the first m inputs of the first, second, third and fourth flip-flops, to the second inputs of which through serially connected fifth eye switch inputs, the first trigger, the second element And the first counter, the first decoder, the N-th output 40 which is connected to the second input. the first trigger, the OR element, the second trigger, the third AND element, the second input of which and the second input of the second AND element are the third input 45 of the switch, the second counter and the second decoder, the output of which is connected to the second input of the second trigger, and the output of the third element And is the output of the switch. ten And the delay line is connected. the output of the fifth flip-flop, to the first input of which the output of the delay line is connected, and the outputs of the first, second, third and fourth flip-flops are respectively the first, second, third and fourth determinant outputs, the seventh and eighth inputs 9. The system according to claim 4, characterized in that the analyzer of the control unit contains the first decoder, 15, the first, second, third and fourth. "The inputs of which are respectively the first, second, third and fourth inputs of the analyzer, the first output of the first decoder through the first A trigger 20 is connected to the first inputs of the second decoder and comparator unit, the outputs of which are connected to the first and second inputs, the key whose output. It is the output of the analyzer25 pa, the second output of the first decoder is connected to the first input of the second trigger, the third output to the second inputs of the first and second triggers, the output of the second trigger is connected to eye switch inputs, the first trigger, the second element And the first counter, the first decoder, the N-th output 40 which is connected to the second input. the first trigger, the OR element, the second trigger, the third AND element, the second input of which and the second input of the second AND element are the third input 45 of the switch, the second counter and the second decoder, the output of which is connected to the second input of the second trigger, and the output of the third element And is the output of the switch. fiyo. 7 8 phage.b f1lg.1 FI5.8 / 2 JV cpue.9