SU1401472A1 - Device for interfacing a computer with selector channel - Google Patents

Abstract

The invention relates to computing and can be used in building a computer network by interfacing a personal computer with a single computer system. The aim of the invention is to increase the speed of data transmission due to the realization of the possibility of connecting a personal computer directly to the selector channel of the main computer, mine the display control unit. This goal is achieved by introducing into the known device for interfacing the exchange control unit 5, the gates block 6, the bi-directional bus driver 7 and the four bus driver shaders 8-11. Dp control device uses a program stored in the personal computer memory. When exchanging data with the personal computer memory, the device for interfacing uses the channel of a typical direct access unit. 7 il. cl

Description

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The invention relates to computing and can be used in building a computer network by interfacing a personal computer with a single computer system.

The purpose of the invention is to increase the speed of data transmission due to the realization of the possibility of connecting a personal computer directly to the selector channel of the main computer, mine the display control unit.

FIG. 1 shows a functional diagram of an apparatus for interfacing a personal computer with a selector channel; in fig. 2 is a sampling unit in FIG. 3 shows a subscriber identity block in FIG. 4 - control unit; in fig. 5 — exchange control unit; Figure 6 shows the gates block in FIG. 7 - algorithm of the program for servicing the interface device.

The device for interfacing the computer with the selector channel comprises a sampling unit 1, a subscriber identifier unit 2, a control unit 3, an output register 4, a unit. 5 exchange control unit 6 gates, bidirectional driver 7, first 8, second 9, third Yu and quarter 11 drivers and has an internal bidirectional data bus 12, first control input 13, information input / output 1A, second control input 15, information input 16, control output 17, interrupt request output 18, information output 19,

Sampling unit 1 (Fig. 2) contains a subscriber address generator 20, sample distribution trigger 21, sample trigger 22, comparison node 23, AND elements 24-31, OR elements 32-34J, sample capture signal output 35, sample trigger output 36 , the output 37 signal of the initial sample (NBR) ..

The subscriber identifier block 2 (Fig. 3) contains a register 38, elements AND 39-42, element OR 43, signal output 44. Remember the state (REC); output 45 RAB-A, output 46 of the demand signal.

The control unit 3 (Fig. 4) contains a selective reset trigger 47, a system reset trigger 48, a data transfer trigger 49, an exchange trigger 50, a stop trigger 51, AND elements 52-58, OR elements 59-65, data transfer direction output 66 from the channel in PC, you

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The path 67 for sending data from VEVM to the channel, the output of the element OR 63 is a general reset, the output of the element OR 64 is the interrupt request to the system bus, the output 68 of the reset signal of the exchange control unit.

The exchange control unit 5 (FIG. 5) contains trigger 69, elements AND 70- 78, exchange end trigger 79, elements OR 80-84, the output of the element OR 83 —the request signal for transferring data over the system bus, the output of the element OR 84 - signal of the end of the exchange, trigger output 69 - INF-A.

The gates block 6 (FIG. 6) contains a decoder 85, elements AND 86-99, elements OR 100-104, output 105 — write strobe to the output register (SHIN-A) 5 output 106 — reading strobe (SHIN-K).

The device control input 13 contains bits 107 - RVB-K, 108-VBR-K, 109 - ADR-K, 110 - BLK-K, 111 - UPR-K, 112 - INF-K, 113 - RAB-K.

The device control input 15 contains bits 114 — an exchange cycle, 115 — an address bus, 116- the end of an exchange, 117 - an address lock, 118- a power-on reset, 119- a write to the port, 120 - a port read.

The device works as follows.

Sampling unit 1 (FIG. 2) determines that the initial sampling sequence is performed on the channel side (the channel has set the address of the PC, ADR-K 109, VBR-K 108, and then RVB-K 107 to the SIN-K 16), excitation output 37, the signal from the output of the element And 31 resets the distribution trigger 21, and when the RVB-K 107 appears, sets the trigger 22 of the sample, which excites output 35, but if the sample is performed on demand, only output 35 is excited, analyzing which the mapper maintenance program determines that it has captured a sample.

Block 2 subscriber IDs. (FIG. 3) is intended to programmatically set subscriber identifiers. Reset of identifiers can also be performed on a general reset signal from control unit 3.

The control unit 3 (FIG. 4) is designed to control the operation of the interface device. The selective reset trigger 47 is set.

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if the channel performs a selective reset of the PC (the BLK-K 110 is installed and the RAB-K 113 is reset). A system reset trigger 48 is set if the channel is performing a system reset (RAB-K 113 and BLK-K 110 are reset). The direction trigger 49 is programmed and determines the direction of the data transfer. The exchange trigger 50 is established in software and permits data exchange between the channel and the PC. A stop trigger 51 is set if the channel issues a disconnect sequence from the interface during data transfer (sets ADR-K 109 and resets the RVB-K 107 and VBR-K 108). A single state of flip-flop 51 causes a flip-flop of flip-flop 50 to be reset, which, in turn, causes a reset control signal 68 to clear. A request to interrupt the system bus from the output of the OR 64 element is generated if either the selective reset of the PC (set trigger 47) or the system reset (set trigger 48) or the initial PC sample (there is a HBRB 37 signal from block 1 sampling)

Output register 4 is intended to set the address of the PC, the data status byte, on the TIR-A.

The exchange control unit 5 (FIG. 5) serves to control the data exchange between the interface device and the channel over the I / O interface and between the interface device and the PC memory on the system bus. The output of the element OR 77 is the request signal for transmission over the system bus, the output of the element OR 78 is the signal of the end of exchange, the output of the trigger 69 is INF-A.

The gates block 6 (Fig. 6) generates reading and writing gates. And signals that control the passage of information through the bi-directional driver 7.

The formers 8-11 are intended for receiving information from the information input to the internal bus 12 of data on reading gates from the block 6 of gates.

To control the device to interface, the PC uses a program that controls the equipment of the device to interface using input and output commands. Output commands are used to set or reset any trigger for

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setting the address of the PC and the byte of the state on ShII-A. Input commands are used to analyze the state of the items of equipment.

The input command transfers a byte from the input port to the PC battery. When the input command is executed by the system bus, the port is read cycle, the port address is placed on the address bus 115, no bus 117 is blocked, and the port reading line 120 is energized. In block 6 of gates (Fig. 6), the signal from the output of element 101 is absent, which configures the bidirectional driver 7 to transmit information from the internal data bus 12 to the information input-output 14 of the device; the signal from the input of the element OR 102 is excited, which controls the output of bi-directional the driver 7, as well as the reading strobe (output of one of the elements 94-97), the information from the output of one of the drivers 8-11 through the reading gate from block 6 enters the data bus 12 and through the bi-directional driver 7 to information input-output 1 4 devices.

- The output command sends a byte from the battery to the output port. When executing a command for outputting by the system bus, a write cycle to the port is performed, the port address is placed on address bus 115, no address bus 117 is blocked, the write line 119 is excited to the port, in block 6 gates the signal from the output of the OR 101 element, which adjusts bidirectional driver 7 for transferring information from information input / output 14 of the device to data bus 12, a signal from the output of the element OR 102, which controls the output of the bidirectional driver 7, is excited, as well as recording strobe (output one and From the elements 91-193, information from the device information input-output 14 through the bi-directional driver arrives on the data bus 12 and at the end of the recording strobe is fixed in one of the blocks 2-4.

For data exchange with the operating memory of the PC, the device for interfacing uses a direct memory access unit (DAP) located on the system board of the PC. Upon request for data transfer from the output of the exchange control unit 5, the RAP organizes data transfer cycles on the system bus between the RAM and the I / O port.

Before you use the RAP, it must be programmed. It means to set the operation mode (Single, on demand), set the direction of data transfer (Write to memory, Read from memory), enter the initial address of the data, and add a byte counter.

The device for pairing uses PDP in a single mode of operation. In this mode, in response to a request for data transfer, one data transmission over the system bus is executed. In a transmission cycle, data bytes are transmitted from the memory to the port or vice versa. The data address in the PDU is modified by +1, the byte count by -1. In the last byte transmission cycle, when the byte counter becomes zero, the end of exchange signal 116 is energized.

A sign that the system bus performs a data transfer cycle under the control of the RAP, is the presence of a signal 114. exchange cycle, which permits in block 6 a hardware write strobe from the output of the And 98 element and a hardware read strobe from the output of the And 99 element, and the presence of a signal 117 address blocking which

blocks gates with elements And 91-97 I

If there is a write signal 119, then a data byte transfer cycle from the main memory of the PC to the output register 4 is performed. The data is read from the main memory to the information input / output 14 of the device, through the bi-directional driver 7 they go to the internal data bus 12 ( Fig. 1) and are written to the VC 4 on gate 105 of the record. If there is a read signal 120, then the data byte from the input 16 of the interface information (BUS-K) to the main memory of the personal computer is executed: the reading strobe 106 queries the driver 8, on the information input of which there is data from the BUS-K 8 get on the internal bus 12 dnnk, through the bidirectional driver 7 - on the information input-output device 14 and in the operational memory of the PC,

The device for resetting the device to the initial state transitions either after a system reset or a selective channel side reset, or after an I / O operation is completed. In the initial state, all the triggers of the control unit 3 are reset. From the output 69 of the control unit 3, the reset signal

Q is fed to the input of the exchange control unit 5 and maintains it in the initial state.

A PC, having in its composition a device for interfacing with a channel,

c represents for the channel the active peripheral device. In order to exchange data with the channel, the interface device transmits to the channel the status bytes with the bit.

 causes an interrupt setting on the channel.

After the interrupt processing, the channel performs the initial PC sample in the Start I / O command in order to

5 to perform the operation of writing data to a PC or reading them from a PC.

The maintenance program of the interface device (Fig. 7) has two inputs. Input 1 (software interrupt input) is used to test the sequence of transmitting a status byte to the channel. Input 2 (hardware interrupt input from the mating device) is used to test

5 sequences of initial sampling and reset sequences (system and selective). I

The service program sets the request bit (TRB) in register 38 (FIG. 3), which causes the appearance of TRV-A at the device control output 17 and loops, waiting for the sample from the channel g, polling driver 11 (BEP bit). Having determined that the channel has sent a sample, the program proceeds to the selection sequence. At the end of the sampling sequence, the program analyzes the response to the UPR-A signal. There are two possible answers. If it is UPR-K, then the program resets UPR-A, waits for the channel to reset the sample signal, resets

g PAB-A, sets the trigger of the ZAP and loops while waiting for a sample from the channel and further, as described above. If it is INF-K, then the program resets the UPR-A, analyzes the sign

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The initial status byte (it is not present) checks whether the channel has taken a sample from the channel and is disconnected from the channel (resets RAB-A), Exits the service program, and the PC loops, waiting for an interrupt from the pairing device.

When the channel starts the sequence of the initial sampling of the PC, the NBRB output 37 of the sampling unit 1 is excited, the signal from which is fed to the input of the control unit 3, from the output of which the interrupt request signal is sent to the system bus. As a result of the interrupt from the pairing device, control is transferred interface devices (input 2). The program determines that the interrupt is caused by the initial sample (by polling the driver 10), sets for itself the sign of the initial status byte and proceeds to perform the probing sample. He remembers the command sent from the channel in the initial sample, having received the INF-K, resets the UPR-A, analyzes the sign of the initial status byte (it is) and proceeds to prepare the RAP: sets the data direction bit on the system bus, the outcome from the command, sent by the channel in the initial sample, puts the data address in the byte counters from the fixed memory area. Next, the program sets the trigger trigger 49 in the control unit 3 (O - data transfer from the PC to the channel, 1 - data transfer from the channel to the PC). The program then sets the exchange trigger 50 and waits for it to be reset. The unit state of the exchange trigger 50 permits the appearance of signals at the outputs 66 and 67, which set the direction of the exchange and permit the issuance of the request signals by the exchange control unit 5.

If output 67 is energized, data transfer from the PC to the channel is performed as follows.

Immediately after installing the exchange trigger 50, a request to transmit data over the system bus is established, and a data byte transfer cycle is performed on the system bus, in which the exchange cycle signal 114 blocks the request to transmit data on the system bus, the data byte from the operational memory is written to output

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register 4 (SHIN-D) on recording gate 105, on the falling edge of which the trigger INFO-A 69 is also set, in response to which the channel is strewed by INF-K 112, through which the INF-A is reset, to which the channel responds by resetting INF-K , which again leads to the installation of a request for data transmission over the system bus and on.

When executing the last byte transfer cycle over the system bus, the exchange end signal 116 in the exchange control block 5 sets the exchange end trigger, the output of which through the OR 80 element blocks the request to transfer data over the system bus, and when the data byte is transmitted to the channel ( INF-C 112), at the output of the And 77 element, an end-of-exchange signal is generated, which will reset the exchange trigger 50 in the control unit 3.

If output 66 is energized, the data transfer from the channel to the PC is performed in the following way.

Immediately after the installation of the exchange trigger 50, an INF-A trigger 69 is installed, to which the channel responds with INF-K 112 and sends a data byte over BUS-K 16. By the coincidence of the signals at the inputs of the element 75, a request for data transmission over the system bus is established. A system bus data transmission cycle is performed, in which the exchange cycle signal 114 blocks the request for data transmission via the system bus, the flip-flop 69 INF-A is reset on the falling edge of the reading strobe 106, to which the channel responds with an IF-112 fault, resulting in to install the INF-A and further as described above.

When executing the last byte transfer cycle over the system bus, the end of exchange signal 79 sets the trigger 79 for the end of the exchange, the output of which blocks the set circuit, the trigger 69 INF-A and the request to transfer data over the system bus. By resetting the INF-K 112, an end-of-exchange signal from the output of the And 78 element is generated, which will reset the exchange trigger 50 in control unit 3. The end-of-exchange signal is terminated in block 5 and by the UPR-K 111 signal.

The program determines the end of the exchange and proceeds to the execution of the sequence of output to the channel of the final state byte, completing which, leads the equipment to its original state.

status and returns to interrupted program

Claims (2)

Invention Formula A device for interfacing a computer with a selector channel containing a subscriber identifier block, a control block, an output register whose information output is an information output of the device, a sampler block whose blocking input is connected to the output of the block sign attribute of the subscriber ID block, the first output bits control unit which is connected to the corresponding bits of the control code of the device, the control output of the sampling unit is connected to the corresponding bit of the control output of the device, The inputs of the control unit of the sample block are connected to the corresponding bits of the first control input of the device, the bits of the input block of the subscriber's identifier block are connected to the corresponding bits of the first control input of the device, the bits of the first input of the control block are connected to the corresponding bits of the first control input of the device , the first reset output of the control unit is connected to the reset input of the subscriber identity block, the second control output of which is connected to the second input of the control unit, v The output reset output of which is connected to the first reset input of the sampling unit, whose address input is connected to the information input of the device, in order to increase the data transfer rate by connecting the personal computer directly to the selector channel of the main computer, mine device display controls, a gates block, a bi-directional bus driver, four bus drivers, an exchange control block, whose reset output is connected to the first reset input of the control block, are inserted into it second reset input of which is connected to the corresponding input of the second discharge control device, the second sampling block reset input connected to a respective input of the second discharge control device, the control unit discharges the entrance gates are connected to rows respectively five 0 five 0 five 0 five 0 55 the UToptiro control input of the control unit, the transmission control output of the gates unit is connected to the transmission control input of the bi-directional bus driver, the first information input / output of which is the information input device of the device, the second information input output of the bi-directional bus driver is connected to the information input of the device subscriber identifiers, with the input of the control information of the control unit and with the information input of the output register, the bits of the first information the second bus driver is connected to the corresponding bits of the first control output of the subscriber identity block, the query output of the sampling block is connected to the request input of the control block, the control output of which is connected to the control input of the exchange control block, the first request output of which is connected to the corresponding control output bit device and to the second information input of the second bus driver, the information input of the third bus driver is connected to the control output control unit, whose request output is connected to the corresponding output of the device interrupt request, the second request output of the exchange control block is connected to the corresponding output of the device interrupt request, the first confirmation input of the exchange control unit is connected to the corresponding bit the first control input of the device, the bits of the second input of the confirmation of the exchange control unit are connected to the corresponding bits of the second control input of the device information, the input of the first bus driver is connected to the information input of the device, the enable input of the first bus driver is connected to the output of the first gate of the gates block and the input of the first gate exchange control unit, the input of the second gate of which is connected to the resolution input of the output register and with the output of the second gate of the gate block, whose outputs from the third to the seventh gate are connected to the inputs V6R-K 77 ej tJ) U.l Fig.Z / J 2 ORIGL / J (PI / 2.S e6iJfodj fnl