SU1387040A1 - Data display - Google Patents

Abstract

The invention relates to automation and computing and is intended to display graphic information on a matrix display panel. The purpose of the invention is to improve the image quality by increasing the brightness of the panel cells. The goal is achieved by the fact that a device containing registers 1, 7, comparison units 2 and 3, synchronization unit 5, counter 6, scanner 9, panel 10, switching unit 11, logic elements 12-14, entered the third register 8, the decoder 4, logical elts 15-22, providing parallel generation of the excitation signals of the horizontal busbars of the panel. 1 il.

Description

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The invention relates to automation and computing and is intended to reproduce graphic data on a matrix gas discharge display panel.

The aim of the invention is to improve the image quality by increasing the luminance of the panel cells and reducing the formation time by image by parallel generation of signals that excite the panel tires.

The ua drawing shows a block diagram of the device.

The device contains the first input i-ii 1, the first 2 and the second 3 comparison blocks, the decoder 4, the synchronization unit 5, the counter 6, the second 7 and the third 8 output registers, the sweep unit 9, the gas discharge display panel 10, the switching unit 11, the element EXCLUSIVE OR 12, first element AND 13, first element OR 14, second 15, third 16, fourth 17, fifth 18, sixth 19 and seventh 20 elements AND, second 21 and third 22 elements OR.

The device works in the following way.

When block 5 generates synchronization of the next pulse at the control input of the input register 1, it writes the n-bit code corresponding to the previous ordinate of the playback process, and the code corresponding to the current ordinate is called at the input. At the moment when the next pulse from the synchronization unit 5 arrives at the input of the scanning unit 9, the next vertical bus of the display panel 10 is connected, the second 7 and third 8 output registers are set to "O" and the formation of signals begins to excite the horizontal buses of the panel.

For this purpose, a pulse sequence is supplied to the input of counter 6, the number of which is equal to half the number of horizontal tires of the display panel 10. The pulses fed to counter 6 generate a "sweep code for the (n-1) -th minus bits of the input and output codes of register 1 The spreading code is fed to one input of blocks 2 and 3 of the comparison, the input and output codes of register 1 are fed to their other inputs. The output signals of the comparison blocks are fed to logic elements 12-14, 17-20, which ensure the generation of control their signals at the information inputs of output registers 7 and 8.

The leading bits of the input and output codes of register 1 are fed to decipher 4, which determines the location of the beginning and end of the segment of the graph reproduced on this column of the display panel 10. If the high bits of the current and previous codes are equal, then

the entire segment of the graph is located in one part of the panel (upper or lower) and the formation of control signals is carried out by the EXCLUSIVE element

OR 12, the first elements are AND 13, OR 14. If the higher bits of the input code are not equal, then one end of the graph segment is located in one part of the panel, and the other in another part. In this case, the formation of control signals is carried out by logic elements 17-20. Let the current and previous values of the input code be equal, then at the output of the first element OR 14 the signal is generated only at the time of coincidence of the scanning codes with the information ones. This signal through the element OR 21 or 22 is fed to the information input of the second 7 or third 8 output registers. Moreover, if the most significant bit of the output code is 1 (0), then a single signal is produced at the first (second) output of the decipher 4, which is fed to the input of the second (third 16) element 15 and provides information to the second (third) 8) the output register 7 pulses received 5 shimn on their sync inputs. Thus, in the excited state there appears an element of the output register, whose output signal through the switching unit 11 provides for the excitation of the horizontal panel width corresponding to the input code.

If only the leading bits of the current and previous input codes are equal, then the EXCLUSIVE OR 12 element, the first e, the AND 13, OR 14 elements of the control will generate control signals to excite all the necessary buses for the playback of image elements. If the spreading code and the lower bits of the current code are equal, the second equalizer 3 generates the equal signal, which is fed to the input of the first element OR 14 and excites the bus of the panel 10 corresponding to the current input code. Signal formation, providing the excitation of the panel tires, located5 between the tires mapped to the current and previous input codes, is carried out by supplying the output input register to the information input of the EXCLUSIVE OR 12 element, providing the extension of the output signals "More (" More and equal to) the first 2 and second 3 comparison blocks. Since the code of each ordinate participates in the formation of the image twice (at first it is current, then previous), when the spinning code and the previous ordinate code are equal, the signal "Equal to the first comparison unit 2, supplied and the inverse input of the first element I, is prohibited

information in the output shift register. As before, the output signal path of the first element OR 14 is determined by the output signal of the decoder 4.

If the current and previous code values are mapped to the tires of the panel 10 located in its various parts, then it is necessary to excite the element of the second 7 or third 8 output registers corresponding to the current value of the input code, as well as elements of the second output register 7 corresponding to smaller than the largest from the current and previous values, the input codes, and the elements of the second output register corresponding to the larger of the smallest values of the input codes. At the current code value greater than the previous one, the necessary cells of the second output register 7 are recovered by the output signal "Less and equal to the third output of the second comparison unit 3, which passes to the information input of this register when the fourth output And 17 arrives at the third output decoder 4. The excitation of the necessary elements of the third output register 8 is provided by the output signal of the sixth element And 19, which is formed as a result of the logical multiplication of the output signal fishing from the third output of the decipher 4 and more from the third output of the first block 2 of the comparison. If the previous code value is greater than the current one, then the formation of signals to excite the necessary elements of the second 7 and third 8 output registers occurs similarly to the output signals of the fifth 18 and seventh 20 elements And while simultaneously lowering the signals from the fourth, the output of the decoder 4 and from the first outputs of the first 2 and second 3 blocks of comparison.

When generating the next signals of the synchronization blocks 5, the sequence of operation of the device nodes is repeated.

Thus, in the proposed device, the generation of control signals for driving the required horizontal busbars is carried out in parallel for the upper and lower parts of the display panel and, consequently, the formation time of the image is halved, which makes it possible to use elements with a significantly lower speed in the proposed device. .

Claims (1)

Invention Formula A device for displaying information comprising a first register whose information input is an input 0 device, and the control input is connected to the first output of the synchronization unit, the second output of which is connected to the clock inputs of the counter and the second register, the third output to the installation input of the second register and the counting input of the scanner, the outputs of which are connected to the vertical glands of the gas discharge display panel, the horizontal buses of which are connected to the outputs of the switching unit, the inputs of the first group of which are connected to the outputs of the second register, the first output and the first information input of the first register are connected with the first inputs of the first and second comparison blocks, respectively, the second inputs of which are connected to the output of the counter, the first outputs of the comparison blocks are connected to the inputs of the EXCLUSIVE OR element, the output of which is connected to the first input of the first And element, the second input of which is connected to the second output of the first comparison unit, and the output with the first input of the first OR element, the second input of which is connected to the second output of the second comparison unit, characterized in that, in order to increase 5 image quality by increasing the brightness of the panel cells, the third register, the decoder, from the second to the seventh elements AND, the second and third elements OR, the first inputs of which are connected to the outputs of the second and 0 of the third And elements, the second inputs are with the outputs of the fourth and fifth And elements, respectively, the third inputs are with the outputs of the sixth and seventh And elements, respectively, the first inputs of which are connected to the output of the first OR element, and the second inputs are respectively with the first and second the outputs of the descrambler, the third output of which is connected to the first inputs of the second and third elements, respectively, the second inputs of which are connected respectively to the third output of the second and the first output of the first comparison unit, the fourth output of the decoder torus connected respectively to the first inputs of the fourth and fifth AND gates, the second inputs of which are connected respectively to the third 5 the output of the first and the first output of the second comparison unit, the inputs of the descrambler are connected to the second input and the second output of the first register, the outputs of the second and third OR elements are connected to the information inputs of the second and third registers, respectively, the clock input of the third register is connected to the second, and the setpoint with the third outputs of the synchronization unit, and the outputs of the third register are connected to the inputs of the second group of the switching unit. 0