SU1385242A1 - Frequency multiplier - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase efficiency at low frequencies of the working range. The device contains an input filter 1, an output filter 2, a semiconductor diode 3, a capacitor 4, A transistor (T) 5 is introduced, the emitter and the collector K are connected to the corresponding diode 3 of the electrodes. The base T 5 is connected to an additional inverse output filter 1, diode 3 and T 5 perform the functions of a controllable key with two-way conductance. Capacitor 4 is used as an electronic device that does not introduce losses and creates a weak form of voltage. The larger the capacitance of the capacitor 4, the greater the amplitude of the voltage pulses, the greater the output power of the device. The base circuit T 5 is constructed according to known rules, it is used to set the operating point in direct current, and also provides communication with the previous cascade. When multiplying the frequency, the base circuit containing resistors 6 and 7 is used at an even number of times. When multiplied by an odd number of times, a bias voltage is introduced into the base circuit T 5, while the base circuit does not contain an element to supply the bias. 3 il. (Oh (L

Description

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The invention relates to radio engineering and can be used as a source of harmonic oscillations, in particular in communication systems,

The purpose of the invention is to increase the efficiency at low frequencies of the working range.

Figures 1 and 2 illustrate the circuit diagram of the proposed frequency multiplier for cases of frequency multiplication, even and odd times, respectively; in fig. 3 - time diagrams of his work.

The frequency multiplier contains an input filter 1, an output filter 2, a semiconductor diode 3, a capacitor 4, a transistor 5,

The frequency multiplier works as follows.

When the oscillation frequency is fed to the input with a frequency o on the capacitor 9 of the input filter 1 (Fig. 1), a sinusoidal voltage appears (Fig. 3a) which, from the additional inverse output of the input filter 1, through a voltage divider composed of resistors 6 and 7 (Fig. 1), is supplied to the base of transistor 5,

Under the action of tensioning IJg, a current ig flows through the inductance coil 8 (Fig. 36). The first quarter of the period T of the input oscillations of the current ig (horizontal hatching in Fig. 36) flows through the semiconductor diode 3, creating a very small voltage value ,,,, (Fig. Sv) is negative. Therefore, despite the fact that at this time a positive voltage is applied to the base of transistor 5, it is closed by a negative voltage iJio-ni applied to the collector. In the second quarter of the period, the current ig (vertical hatching in Fig. 36) flows through the transistor 5, creating an insignificant positive voltage c-ti (Fig. Sv) at terminals 10 and 1J, which blocks semiconductor diode 3. Secondly half of the period T, the current ig (sloping hatch in Fig. 36) flows through the capacitor 4, creating a voltage of about -1 on it (Fig. Sv). At this time, the semiconductor diode 3 is closed by a positive voltage

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and the transistor 5 is the negative voltage U, supplied through the resistive divider 6 and 7 of the voltage to its base.

Thus, the input of the output filter 2 is supplied with voltage c,., (Fig. "Sv, solid line), in the spectrum of which high harmonics are contained. Under the action of voltage ig, a current of the M-th harmonic flows through the input circuit of the output filter 2 (Fig. 3g, where the multiplication factor M is equal to two) and the output of the output filter 2 directs the voltage of the multiplied frequency.

The capacitor 4, the semiconductor diode 3 and the transistor 5 collectively represent a non-linear two-port circuit, through the terminals 10 and 11 of which, in the steady state, charge q flows (dotted line in Fig. H), equal to the sum of the charges FD and q., and on its clamps 10 and 11, a voltage, L ,,,, (dotted in Fig. Sv), is created: the shape of which can be explained as follows. In the proposed multiplier, the frequencies of the semiconductor diode 3 and the transistor 5 perform the functions of a controlled switch with two-sided conductivity. In the first half of the period, T kLiuch is closed, and the voltage drop and., Is close to zero on it. In the second half of the period T, the switch is open, and charge q (dotted line in fig. Zd) flows through capacitor 4. Since the voltage on capacitor 4 is proportional to the charge, the voltage lo.i-, (dotted line in fig. 2c) retains the form of charge, i.e. It works in the same mode in which diodes with accumulation of charge work when the frequency multiplies, which allow to obtain an efficiency of the multiplier close to 100%. However, with decreasing frequency, diodes with an accumulation of charge begin to behave like rectifying diodes. Therefore, introducing into the multiplier circuit of transistor 5, which provides current flow in the other direction, contributes to maintaining such a mode ps6oTbii in which the ig and Ji currents flow through the terminals 10 and 11, does not contain a constant component, therefore the power of the latter is zero, which contributes to the growth of the CTDT ,

Capacitor 4 is used as an element, not contributing and (losing and creating

The distorted voltage .f 10-111 of FIG. Sv) In this case, the larger the capacitance C of the capacitor 4, the greater the amplitude of the voltage pulses, the greater the power at the output of a T4 multiplier.

The basic circuit of transis-aor 5 is constructed according to well-known rules, it is used to set the operating point ps DC, and also provides communication with the previous cascade. For example, when the frequency is multiplied by an even number of times (FIG. “1), a base circuit containing resistors 6 and 7 is used.

When the frequency is multiplied an odd number of times, a constant bias voltage is introduced into the base circuit of transistor 5 (Fig. 2), while the base circuit does not contain elements for bias supply. The need for bias voltage supply is explained as follows. In the absence of displacement, the voltage pulses (Fig. 3 Sv) have a cut-off angle of 90 ° and therefore, its spectrum contains, in addition to the first, only even harmonics, which indicates the impossibility of multiplying the frequency by an odd number of times. If the base of the transistor 5 to apply the bias voltage, the cut-off angle

The voltage changes and the voltage pulses io-ii will be longer or less than half the period in duration. This will result in the appearance of odd harmonics in the voltage spectrum, ,,, and, therefore, through the code filter 2, made for example in the form of a series circuit tuned to an odd harmonic, current flows, which indicates that the frequency is multiplied an odd number of times.

Claims (1)

Invention Formula A frequency multiplier comprising an input filter, an output filter, a semiconductor diode that is connected in parallel with the output of the input filter and the input of the output filter, as well as a capacitor, one output of which is connected to one of the electrodes of the semiconductor diode, characterized in that frequencies of the operating range, a transistor is inserted in it, the emitter and collector of which is connected to the corresponding of the electrodes of the semiconductor diode, and the base of the transistor is connected to an additional inverse output input filter. 3 “4 FIG. 2 but and 10-11, at / , "- / l / / h / Phie.