SU1383335A1 - Device for comparing numbers - Google Patents

Abstract

The invention relates to automation and computing and is intended to compare three binary numbers with a choice of the maximum, minimum or average of them. The purpose of the invention is to expand the functionality by determining the minimum of the compared numbers. The device contains n blocks 1 (- 11, analyzes, information inputs 2 - 4, inputs 6-8 controls and a decoder 5, each analysis block contains a code generation unit consisting of three AND elements and OR elements, and three bit comparison nodes , each of which contains two AND-NOT elements, elements .OR, NOT, and a depotfrarator contains three NOT elements, an AND element, and three result formation nodes, each of which consists of four AND elements and an OR element. A device for comparing numbers due to pairwise comparison of numbers in comparison schemes, The remaining of the comparison comparison nodes enclosed in the analysis and subsequent decoding of the output transfer states of the pairwise comparison circuits, depending on the task, allow you to choose either the maximum, or the minimum, or the average value of the compared numbers. —ly, 3 dw., 2 tab.

Description

The invention relates to automation and computing and is intended to compare three binary numbers with a choice of the maximum, minimum or average of them.

The purpose of the invention is to expand the functionality by determining the minimum of the compared numbers.

Figure 1 shows a block diagram of a device for comparing numbers; figure 2 is a functional diagram of the i-ro block analysis; on fig.Z - scheme of the decoder.

The device contains n analysis blocks 1, ..., 1, 1, information inputs 2-4 of the compared numbers A, B, C, respectively, decoder 5, control inputs 6-8 (m, n, k), bus 9 logical unit, the first information outputs 10 of the device, the second output of 1 device of equality of numbers, the outputs 12-14 of the decoder 5.

The first analysis block contains a code generation unit consisting of AND 15-17 elements and an OR 18 element, the first, second and third bit comparison nodes, consisting respectively of the OR 19-21 elements, the first 22-24 and the second 25-27 elements and NOT and elements OR NOT 28 - 30.

The decoder contains the elements NOT 31 - 33, the element AND 34, the first, second and third nodes of the formation of the result, consisting respectively of the first 35 - 37, the second 38 - 40 third 41 - 43 and fourth 44 - 46 elements AND, elements OR 47 - 49.

The device works as follows.

Consistently included; e bitwise comparison nodes of the analysis blocks 1, 1,2, ..., 1 fi are the actual comparison schemes of pairs of compared numbers A and B, B and C, and C A. These pairwise comparison schemes of numbers at its outputs P ,,, 1 (, + (of the transfer, a signal is generated: a logical unit, if the first number of the pair is greater than or equal to the second number of the pair, and a signal of a logical zero, if the first number is less than the second.

The principle of operation of the comparison circuit is that the result of the comparison of number codes is determined, starting from the higher bits. If older bits of a pair of numbers have

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its information inputs are signals of different levels, then the comparison result is determined by the output state of the last bit comparison node p „, (q„, Dn,), i.e., if the information input of the first number of the pair contains a signal of a logical unit (zero, and at the information input of the second number of the pair is a logical zero (one), then at the output of the last comparison node the signal of a logical unit (zero) is independent of the transfer input of the last comparison node p (-q, l). informational inputs of the last comparison the same signal levels, then the Pc41 output (Cp4g I4 transmits a signal present at the input p (q, 1) of the transfer. If a part of the higher bits of the numbers being compared is equal to the output of the comparison circuit, - a regular comparison node, on the information inputs of which there are different signal levels. If the numbers being compared are equal, then a single signal from the bus 9 of a logical unit is transmitted to the code P ,, (q ,,, 1 „„).

The combination of the output signals of the PMD PE + 1 if the outputs of the comparison circuits carries information about the relationship between the compared numbers. Therefore, the output signals pn ,, .mk nocTjmaioT to the information inputs of the decoder, which, according to the task, determines the number that is sent to the information output 10 of the device X (the task is to select the maximum, minimum or average numbers). The selection of the maximum, minimum or average values of the compared numbers is carried out using signals at the control inputs 6-8 of the device,

To extract the maximum value of the device control input 6, a logical unit signal is applied to the m input of the decoder 5, while the decoder inputs n, k are logic zero, Dp the minimum value from the compared numbers of the logical unit signal is fed to the device control input 7, which arrives at the input n of the decoder 5 at the same time mk 0. For the selection of the average

the value at the input 8 of the control unit receives the signal of the logical unit to the input k of the decoder (m n n 0).

In tab. Figure 1 shows the logical levels of the signals at the outputs of the transfer of the comparison circuit. Pairs of the compared numbers p, ,, q, 1, depending on the relation between the compared numbers.

Table 2 shows the logical levels of the signals at the outputs 12-14 of the decoder 5 and the number at the information output 10 of the device X depending on the state of the information inputs Phu q In1 PCh and the control inputs m, n, k of the decoder.

The signal of a logical unit is present simultaneously on all information inputs p ,, q ,, 1, decoder 5 only in one case when the compared numbers are equal to each other. This case is highlighted on AND 34 of the decoder, p. which a single signal follows the third control output of the decoder 14 and the output 1 1 of the device.

A group of outputs 12–14 of the decoder should go to the control inputs of the analysis block 1,, 1, ..., 1 and determine which of the compared numbers to be transferred to the information output of the device X. If the output 12 of the decoder is excited, then the output X A number is transmitted to the device, if output 13 is excited - number B, output 14 is number C.

In case of equality of three numbers

the output 14 of the decoder is excited, the output of the element AND 34 through the element OR 49 and the output C of the device transmits the number C (in this case, in principle, any of the compared numbers can be transmitted to the output X of the device).

Claims (2)

1. A device for comparing numbers, containing n analysis units, where n is the size of the equalized numbers, each of which includes a code generation unit containing the first, second and third AND elements and the OR element, the first, second and third comparison nodes, each of them five 0 5 about 0 - five 0 includes the OR element, with the first, second and third information inputs of each analysis block being the inputs of the corresponding bits of the first, second and third numbers of the device, respectively, in each analysis block the first, second and third information inputs are connected to the first information inputs of the first, second and third bit comparison nodes, respectively, the first control inputs of the analysis blocks are combined, the first, second and third transfer outputs of the i-ro analysis block, which are the transfer outputs of the corresponding of the comparison nodes, where i 1,2, ..., p-1, are connected respectively with the first, second and third transfer inputs of the (i + l) -ro analysis block, respectively, which are the transfer inputs of the first, second and the third. Comparison comparison nodes, the transfer inputs of the first analysis block are connected to the inputs of the logical unit of the device, the outputs of the OR elements of the code generation blocks of the analysis blocks are the information outputs of the device, in each code forming node the outputs of the first, second and third elements connected to the entrances of u OR, characterized in that, in order to extend the functionality by determining the minimum of the compared numbers, a decoder is entered into it, at each j-th and bit comparison node, where j 1,2,3, each analysis block is entered first and the second AND-NOT element and the OR-NOT element, the first output of the decoder is connected to the first control inputs of the analysis blocks, in each analysis block the first control input is connected to the first input of the first AND element of the code generation unit, the second and third decoder outputs are connected to The first inputs of the second and third elements, respectively, of the nodes forming the codes of all the analysis units, the transfer outputs of the nth analysis block are connected to the corresponding information inputs of the descrambler, the first, second and third control inputs of which are the device mode setting inputs, the fourth output of the decoder equality of device numbers, first The second and third information inputs of each analysis block are connected to the second inputs of the first, second and third elements AND of the code generation unit in each analysis block, respectively; the second information input of the j-ro bit comparison node is connected to (j + l) -M information input of the block analysis, except for the second information input of the third bit comparison node, which is connected to the first information input of the analysis unit, and in JM the bit input of the comparison node NIN the first input of the first AND element is NOT the first information The memory input of the bit comparison node is connected to the first input of the OR-NOT element, the second input of which, which is the transfer input of the bit comparison node, is connected to the second input of the first AND-NE element whose output is connected to the first input. the second element is NAND, the second input is connected to the output of the element OR, the first input of which is connected to the output of the element OR NOT, the second input of the element OR the second information input of the one-way comparison, the output of which is the output of the second element AND NONE . 2. The device according to claim 1, about tl and - that the decoder contains the first, second and third elements NOT, the element I, the first, second and third nodes of the formation, each of which includes the first, second, third and the fourth AND elements and the OR, whose output is the corresponding output of the decoder, the first control input of the decoder is connected to the first inputs of the first elements AND the result setting nodes, the first inputs of the second elements AND of which are connected to the second control input of the decoder, the third control input d is connected to the first inputs of the third and fourth members and the result forming units, the second inputs of the first and third elements of the first node and generating a result, the second and fourth elements and forming a second node ten 15 20 25 thirty 35 40 45 50 55 the result and the fourth element And the third node forming the result is connected to the first input of the element And and the first information input of the decoder, through the first element is NOT connected to the second inputs of the second and fourth elements And the first node forming the result, the first and third elements And the second node forming the result and The third element a AND the third node forming the result, the second information input of the decoder is connected to the second inputs of the element And the second element And the third node forming result and with the third inputs of the fourth element AND the first node forming the result, the first and fourth elements AND the second node forming the result and the third element AND the third node forming the result, and through the second element NOT with the third inputs of the third element AND the first node forming the result, the second and third elements AND the second node forming the result, the fourth element AND the third node forming the result and the second input of the first element AND the third node forming the result, the third information input decoder a is connected to the third inputs of the element And the second element And the first node forming the result, the first element And the third node forming the result, with the fourth inputs of the third element And the first, second and third nodes forming the result, and through the third element NOT with the third inputs The first element And the first node forming the result of the second element And the third node forming the result and with the fourth inputs of the fourth elements And the first, second and third nodes forming The result, the outputs of each element AND the result generation node are connected to the corresponding inputs of the OR element of the same result formation node, and the output of the AND descriptor element is connected to the fifth input of the OR element of the third result formation node and is the fourth output of the decoder. Table 1 Table 2 u, z / eleven Fig.Z