JPH039498B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output device for a programmable controller, and more particularly to an input/output device that can exchange input/output data with a controller main body by serial data transmission.

Recently, relatively large-scale centralized control systems using programmable controllers are often seen in control systems for general mechanical plants and the like. In such a centralized control system,
In many cases, various input devices, such as limit switches, temperature switches, proximity switches, photoelectric switches, etc., and various output devices, such as motors, plungers, solenoid valves, etc., are each connected to a central control device by separate signal lines. In this case, in systems where there are a large number of these input/output devices and each input/output device is distributed over a relatively wide space, the wiring space and wiring cost that connect each input/output device and the central control unit become a major problem. Therefore, there is a strong desire to simplify signal transmission during this time by applying appropriate multiplex transmission.

Various multiplex transmission systems have been known in the past, and some have been used to transmit input/output data in programmable controllers. However, in the conventional multiplex transmission system, a unique address is assigned to each terminal, and each terminal has a circuit for determining the address, and the transmission control procedure including this address determination circuit is extremely complicated and sophisticated.
Therefore, it is an expensive device. Of course, there is some significance in using such an advanced circuit system, but
The input/output data transmission system in the programmable controller has many unnecessary functions, and therefore cannot adequately meet the above-mentioned demands.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to configure an input/output device separately from the controller main body, and to connect the necessary number of input/output devices to the controller main body by serial data lines. By simply connecting with two signal lines, the and clock signal line, there is no need for an address discrimination circuit on the input/output device side, and output data can be transferred from the controller main body to the input/output device without going through troublesome transmission control procedures. Another object of the present invention is to provide an input/output device for a programmable controller that allows input data to be transmitted from the input/output device to the controller main body.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

Figure 1 shows a programmable system to which this invention is applied.
1 is a block diagram showing the overall schematic configuration of a controller system. FIG. This programmable controller is divided into a controller body 1 and a plurality of input/output devices 2, 2, . . . . In this embodiment, a plurality of input/output devices 2, 2,...
have exactly the same configuration. Each input/output device 2 is connected to various input devices such as limit switches 4
It has two input terminals and four output terminals to which various output devices such as motors and plungers are connected. The signals applied to each input terminal are called external input signals, and these signals are applied to IN1 to IN4, IN5 to IN8, IN
Assign a different number from 9 to IN12. Similarly,
The signal output from the output terminal of the input/output device 2 is called an external output signal, and this signal is
4. Assign separate identification numbers to OUT5 to OUT8 and OUT9 to OUT12.

The controller body 1 includes a CPU 3 (central processing unit) that serves as the center of overall control, a system program memory 4 that stores system programs executed by the CPU 3, and a temporary storage area for various variable data by the CPU 3. A system data memory 5 to be used, a user program memory 6 in which a sequence control program arbitrarily set by the user is stored, and an input/output memory serving as a buffer memory for input/output data corresponding to external input/output signals in the input/output device 2. It is provided with a memory 7 and an input/output port 8 serving as an interface for providing output data from the controller main body 1 to the input/output device 2 and for taking input data from the input/output device 2 into the controller main body 1.

As is well known, the execution operation of a user program in this type of programmable controller basically involves sequentially reading out user instructions from the user program memory 6, and executing the input/output memory 7 stored in the input/output memory 7 according to each user instruction. It is to perform arithmetic processing between output data and update the output data in the input/output memory 7 according to the result of the calculation,
In addition, an input update operation that writes input data from the input/output device 2 to a predetermined area of the input/output memory 7 in synchronization with the execution of the user program, and transfers output data of the predetermined area of the input/output memory 7 to the input/output device 2 An output update operation is performed, and as a result, a sequence state specified by the user program is created in the relationship between the input data applied to the input/output device 2 and the output data outputted from the input/output device 2. The input/output data transmission according to the present invention is the input/output data transmission performed between the controller main body 1 and the input/output device 2 in order to perform the above-mentioned input update operation and output update operation.

The controller body 1 includes a serial data input/output terminal SDT and a clock signal output terminal CKT as terminals for data transmission. The signal applied to the serial data input/output terminal SDT is the receiver 9
is applied to input port P1 via. The signal from the output port P2 is outputted to the serial data input/output terminal SDT via the driver 10. This driver 10 is inhibited by a signal from output port 3. The clock signal output from output port P4 is connected to driver 1 at clock signal output terminal CKT.
1.

The input/output device 2 has a left serial data input/output terminal SDL, a right serial data input/output terminal SDR, and a clock signal input terminal as terminals for data transmission.
Has CKL. The three input/output devices 2 have their right serial data input/output terminal SDR and left serial data input/output terminal SDL connected to each other by a serial data line 12, and each other's clock signal input terminal CKL to each other by a clock signal line 13. , these two transmission lines 12,1
3, the three units are connected in series. Also, the left serial data input/output terminal of the leftmost input/output device 2
SDL is also connected to the serial data input/output terminal SDT of the controller main body 1 by a serial data line 12,
The clock signal input terminal CKL is also connected to the clock signal output terminal CKT of the controller body 1 via a clock signal line 13. That is, the three input/output devices 2 are connected in series to the controller body 1 via the serial data line 12, and are connected in parallel to the clock signal line 13. Further, the right serial data input/output terminal SDR of the rightmost input/output device 2 is opened, and another input/output device 2 can be further connected in series to this open right serial data input/output terminal SDR.

FIG. 2 shows a detailed circuit diagram of one input/output device 2. As shown in FIG. As shown in the figure, this input/output device includes a 5-bit unidirectional shift register 14,
A latch circuit 15 connected to parallel output terminals Q1 to Q4 of bits 1 to 4 of this shift register 14.
The output of this latch circuit 15 is used as an external output signal.
A driver 16 that outputs outputs in parallel as OUT1 to OUT4, and a receiver 17 that receives external input signals IN4 to IN1 in parallel and applies them to the parallel input terminals D1 to D4 of the 1st to 4th bits of the shift register 14.
and the 5th bit input terminal D of the above shift register
5, a receiver 19 that receives a signal applied to the left serial data input/output terminal SDL, and a left serial data input/output terminal.
Gated driver 20 that sends a signal to SDL
, a receiver 21 that receives a signal applied to the right serial data input/output terminal SDR, a gated driver 22 that sends a signal to the right serial data input/output terminal SDR, and a signal applied to the clock signal input terminal CKL. The signal applied to the receiver 23 and the left serial data input/output terminal SDL is used as the serial input SI of the shift register 14, and the serial output obtained from the 4th bit output terminal Q4 of the shift register 14 is used as the right serial data input. Either the output terminal SDR or the signal applied to the right serial data input/output terminal SDR is set as the serial input SI of the shift register 4, and the serial output obtained from the 5th bit output terminal Q5 of the shift register 14 is set as the serial input SI of the shift register 4. A switching circuit (the gated driver 2
0, 22 and logic gates G1, G2, G3) and a clock signal input terminal.
a control circuit 18 that detects that the level of the signal applied to CKL is fixed for a certain period of time or more and generates a latch signal for the latch circuit 15, a parallel input read signal for the shift register 14, and an inverted signal for the switching circuit; Equipped with.

The signal applied to the clock signal input terminal CKL is received via the receiver 23, is signaled as the shift clock signal CK of the shift register 14, and is input to the control circuit 18.

In the control circuit 18, when the period of the clock signal outputted from the controller body 1 to the clock signal line 13 is TO, the clock signal is stopped and the signal level of the signal line 13 is fixed at H level or L level. This is to detect that a certain period of time T1 or more, which is sufficiently larger than the clock period TO, has continued. This detection is performed by an EOR circuit 25, a timer circuit 26, and a flip-flop 27. Flip-flop 27 is initially reset by power-on reset circuit 50 when power is turned on. The output Q of the flip-flop 27 and the output signal a of the receiver 23 (signal on the clock line 13) are input to the EOR circuit 25, the output signal b of which is input to the timer circuit 26, and the output signal c of the flip-flop 27 causes the flip-flop 27 to be activated. It is now controlled in reverse.

The timer circuit 26 outputs an output signal c and inverts the flip-flop 27 when the input signal b goes to the L level and remains at the L level continuously for the above-mentioned fixed time T1. Therefore, when the flip-flop 27 is set and Q=H, the timer circuit 26 outputs the clock signal line 13.
The flip-flop 27 acts to detect when the signal a of
When Q is reset and Q=L, it acts to detect that the signal a on the clock signal line 13 has been fixed at the L level for a period of time T1 or longer.

The output of the flip-flop 27 becomes a control signal for the switching circuit. In other words, flip-flop 27
has been reset and Q=L,=H,
The driver 20 and logic gate G2 are disabled, and the driver 22 and logic gate G1 are activated. In this state, the left serial data input/output terminal
The signal applied to SDL is input to the serial input terminal SI of the shift register 14, and the signal from the serial output terminal Q4 of the shift register 14 is led to the right serial data input/output terminal SDR. On the contrary, flip-flop 27 is set, Q=H,=L
In this case, the signal applied to the right serial data input/output terminal SDR is inputted to the serial input terminal SI of the shift register 14, and the signal from the serial output terminal Q4 of the shift register 14 is applied to the left serial data input/output terminal.
Derived to SDL.

Furthermore, the rise of the Q output of the flip-flop 27 to the H level is detected by a differentiation circuit 28 for rising edge detection, and the output pulse of this differentiation circuit 28 is applied as a latch signal T to the latch circuit 15. The Q output of the flip-flop 27 is connected to the delay circuit 2.
9, the delayed output is input to a differentiating circuit 30 for detecting a rising edge, and this differentiating circuit 30
An output pulse from the shift register 14 is applied as a parallel input read signal LD to the shift register 14.

Next, the transmission operation of input/output data on the controller main body 1 side will be explained. Controller body 1
is from port P4 of input/output port 8 to driver 1
A predetermined number of clock signals are sent to the clock signal line 13 via the clock signal line 13 to shift the shift register 14, and at the same time, output data is sequentially serially transmitted from the port P2 to the serial data line 12 via the driver 10 in synchronization with this. By outputting to PH, these output data PH are set in the shift register 14, and
After that, the level of the clock signal line 13 is maintained for a certain period of time T.
By fixing 1 or more, the above shift register 1
The output data set to 4 is latched in the latch circuit 15, and the receiver 1
7 is read into the shift register 14, the switching circuit is inverted, and then a predetermined number of clock signals are sent to the clock signal line 13 to shift the shift register 14 again. The controller operates to sequentially input the input data into the controller main body 1 from the port P1 of the input/output port 8 via the serial data line 12 and the receiver 9. This operation is performed by the CPU 3 executing an input/output data transfer routine stored in the system program memory 4.

Further, the controller main body 1 can know how many input/output devices 2 are connected as described below. In other words, in this programmable controller system, if the maximum number of input/output devices 2 that can be connected to the controller main body 1 is N, it is not always necessary to connect N input/output devices 2, but it is necessary to connect the input/output devices 2 according to the user's needs. Depending on N
Any number of input/output devices 2 below can be connected. If only M input/output devices are connected, which is less than N, in order to reduce the input/output data transmission time by that small amount, only the transmission control for the M connected devices is performed. The purpose of this is to know how many input/output devices 2 are connected.

As is clear from the previous explanation, when sending output data from the controller body 1 to the input/output device 2, the left serial data input/output terminal of the input/output device 2
SDL is connected to the serial input terminal SI of the shift register 14, and the serial output terminal Q4 of the shift register 14
is connected to the right serial data input/output terminal SDR, and at this time, when viewed from the input/output terminals SDL and SDR, the shift register 14 operates as a 4-bit shift register. When input data is sent from the input/output device 2 to the controller body 1, the right serial data input/output terminal SDR is connected to the serial input terminal SI of the shift register 14, and the serial output terminal Q5 of the shift register 14 is connected to the left serial data input/output terminal SDR. Connected to the data input/output terminal SDL, and at this time both input/output terminals
The shift register 14 operates as a 5-bit shift register between SDR and SDL.

When transmitting input data in which the shift register 14 operates as a 5-bit shift register,
The parallel input signals D1 to D5 read into the shift register 14 by the parallel input read signal LD are read in the order of D5 → D4 → D3 → D2 → D1 in synchronization with the clock signal applied to the clock signal input terminal CKL. Output from serial data input/output terminal SDL.
Here, as shown in Figure 2, IN4 is in D1,
D2 has IN3, D3 has IN2, D4 has IN
1 is input to each of them, and an H level signal is always input to D5 as described above. Therefore, of the 5-bit serial data outputted from the serial output terminal Q5 of the shift register 14 to the left serial data input/output terminal SDL, the first bit is always an H level signal, and then the signal changes from IN1 to IN2. →IN3→IN
4 4-bit external input signals are output in order.

On the other hand, as shown in FIG. 2, the input side of the receiver 21, which receives the signal applied to the right serial data input/output terminal SDR, is pulled down to the ground potential by a resistor 60, and the right serial data input/output terminal
The subsequent input/output device 2 is not connected to the SDR,
If this terminal SDR is open, receiver 2
1, an L level signal is input. Therefore, other devices 2 are installed after the input/output device 2 shown in FIG.
is not connected, shift register 14
After the parallel input read signal LD is given to the terminal
When five clock signals are applied to CKL, 5-bit serial data is output to the left serial data input/output terminal SDL in the order of H level signal → IN1 → IN2 → IN3 → IN4. Then the terminal
When five clock signals are applied to CKL, the L level signal from the released right serial data input/output terminal SDR side is transferred to the left serial data input/output terminal.
It will be output to SDL.

Therefore, every time the controller body 1 outputs five clock pulses, the input data input in synchronization with the first pulse is either H data or L data.
Depending on the level, it can be determined whether the input/output device 2 is connected or not.

FIG. 3 is a flowchart showing an overview of the above-mentioned input/output data transmission routine executed by the controller body 1. As shown in FIG. Data transmission operations will be explained in order according to this flowchart. The first data transmission starts from step 301.
In step 301, the maximum number of connectable input/output devices 2 is connected to the controller main body 1.
Set the address 4N of the last output data.
In the next step 302, output port P4 is set to L level. In the next step 303, the output data of the set address is output from the output port P2. At this time, it goes without saying that the driver 10 is activated by the signal from the output port P3.

In the next step 304, the signal at the output port P4 is set to H level. In the next step 305, time T, which is somewhat shorter than the period TO of the clock signal, is counted. At step 306 after T time has elapsed, the signal at output port P4 is set to L level. next step
In 307, it is determined whether transmission up to output data OUT1 has been completed. If the transmission has not been completed, proceed to step 308 and set the address of the output data to 1.
and set the address of output data OUT (4N-1). Then, the process returns to step 303.

Above steps 303→304→305→306→307→308
is repeated for the output data OUT(4N) to OUT1, so that each output data is output from the controller main body 1 in synchronization with the clock signal.

When the above-described output data transmission operation is completed, the process proceeds from step 307 to step 309, and the signal at output port P4 is set to H level. In the next step 310, the time T1 required to operate the control circuit 18 is counted. As a result, the signal level of the clock signal line 13 is fixed at the H level for more than T1 time, the control circuit 18 is operated, and the output data set in the shift register 14 is latched in the latch circuit 15 and the driver At the same time, the input data from the receiver 17 is read into the shift register 14, and the connection relationship of the switching circuit is reversed.

On the controller main body 1 side, in the next step 311, the address of the first input data IN1 is set.
In the next step 312, the process waits for the delay time T2 of the delay circuit 29. Further, the driver 10 is inhibited by a signal from the output port P3. In the next step 313, the connected number counter m of the input/output device 2 is cleared. In the next step 314, the input port P
Read the input data to be applied to 1. next step
At step 315, it is determined whether the input data is at H level or L level. As explained above, the fact that this first input data is at H level means that the first input/output device 2 is connected. In that case, proceed to step 316 and clear the quaternary counter K. In the next step 317, the signal at the output port P4 is set to L level. In the next step 318, the above-mentioned time T is counted. In the next step 319, the signal at the output port P4 is set to H level. In the next step 320, the input data applied to the input port P1 is read and stored at the set address.
In the next step 321, the connected device number counter m is incremented by 1. In the next step 322, the set address is incremented by 1. In the next step 323, the quaternary counter K
Add +1 to In the next step 324, it is determined whether the quaternary counter K has counted up. If the count is not up, the process returns to step 317.

By repeating steps 317-324 four times, the 4-bit input data IN1-IN4 of the first input/output device 2 is taken into the controller body 1 and stored at a predetermined address.

When the quaternary counter K counts up,
Returning to step 314, the input data applied to input port P1 is read. Then, in the same way as above, it is determined whether the input data is at H level or L level. This input data is at H level because
This means that the second input/output device 2 is connected. In that case, proceed to step 316 and
In exactly the same way as the second input/output device 2, the input data
IN5 to IN8 are read and stored at a predetermined address, and the connected unit number counter m is incremented by 1 each time input data is read.

When three input/output devices 2 are connected as shown in Fig. 1, the number of connected devices counter m is "12".
When the process returns from step 324 to step 314, the next step 315 detects that the input data read in step 314 is at the L level. That is, it is detected that the fourth input/output device 2 is not connected. In this case, proceed from step 315 to step 325, and output port P4.
signal to L level. In the next step 326, the time T1 required to operate the control circuit 18 is counted. This returns the control circuit 18 and the switching circuit to their initial states. As a result of this first operation, m=4×M is counted in the connected device number counter m, where M is the number of connected input/output devices 2. When transmitting input/output data for the second and subsequent times, the process starts from step 327 instead of from step 301. In other words, when sending output data from the controller main body 1, the address of the last output signal of the actually connected input/output device 2 is set, and the output data is sent while decrementing the address from there. Become. Therefore, it is possible to completely eliminate the meaningless time required to send output data to unconnected input/output devices 2.

As explained in detail above, according to the programmable controller input/output device according to the present invention, the controller main body and the required number of input/output devices are simply connected using two signal lines, a serial data line and a clock signal line. This allows bidirectional signal transmission of input data input and output data transmission, making the installation of transmission lines extremely simple and inexpensive. In addition, the input/output device does not need a circuit to judge addresses or a control circuit to handle complicated transmission control procedures; it simply detects when the clock signal is stopped and the clock signal line level is fixed above a certain level. It is only necessary to provide a very simple control circuit consisting of a timer circuit for detection, a flip-flop, etc., and the configuration of the transmission control section in the input/output device is extremely simple, and it can be manufactured at low cost. In particular, the present invention is inexpensive because it is constructed using a unidirectional shift register which is considerably cheaper than a bidirectional shift register.

Furthermore, the present invention is configured so that the number of connected input/output devices can be known on the controller main body side, so that the input/output data transmission time can be adjusted to match the number of input/output devices actually connected. This has the effect of reducing the amount of time to a minimum.

[Brief explanation of the drawing]

Figure 1 shows a programmable system to which this invention is applied.
FIG. 2 is a block diagram showing the general structure of the controller system, FIG. 2 is a block diagram showing the specific structure of the input/output device, and FIG. 3 is a flowchart showing the outline of the input/output data transmission routine executed by the controller main body. 1... Controller main body, 2... Input/output device,
12...Serial data, 13...Clock signal line,
14...Shift register, 15...Latch circuit,
16...driver, 17...receiver, 18...
Control circuit, SDL...left serial data input/output terminal,
SDR...Right serial data input/output terminal, CKL...Clock signal input terminal, SI...Series input terminal, Q4...
...Series output terminal, Q1-Q4...Parallel data output terminal, D1-D4...Parallel data output terminal, D1-D
4...Parallel data input terminal, LD...Parallel data read signal.

Claims (1)

[Claims] 1 Two serial data input/output terminals A and B,
Connected to a clock signal input terminal, a (X+1) bit shift register that is shifted in only one direction by the clock signal applied to this clock signal input terminal, and a parallel output terminal of 1 to X bits of this shift register. a latch circuit, a driver that derives the output of the latch circuit in parallel as an external output signal, a receiver that receives an external input signal in parallel and applies it to parallel input terminals of bits 1 to X of the shift register; Shift register (X+
1) A circuit that always applies an H level signal to the input terminal of the bit, and a circuit that inputs the signal applied to the input/output terminal A as a series input to the shift register, and outputs a serial signal obtained from the output terminal of the X bit of the shift register. Either the output is led to the input/output terminal B, or the signal applied to the input/output terminal B is connected to the serial input of the shift register and the (X
+1) A switching circuit that switches the serial output obtained from the bit-th output terminal to the input/output terminal A, and detects that the level of the signal applied to the clock signal input terminal is fixed for a certain period of time or more. and a control circuit for producing a latch signal of the latch circuit, a parallel input read signal of the shift register, and an inverted signal of the switching circuit.