SU1381487A1 - Device for adding in redundant binary notation - Google Patents

Abstract

The invention relates to the field of automation and computing. The purpose of the invention is to simplify the device and increase its speed. The device for adding in the redundant binary number system contains the first, second, third, fourth information inputs 1, 2, 3, 4, three delay elements 5, 6, 7, block 8 for forming an intermediate result, block 9 for forming the final result, outputs 10, 11 device results. 2 silt, 2 tabl ..

Description

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four

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figure 1

The invention relates to computing and can be used in computers and devices operating in a redundant binary number system with the numbers 1, 0, 1.

The purpose of the invention is to simplify the device and increase its speed.

FIG. 1 shows a functional diagram of the proposed device; FIG. 2 — an intermediate result generating unit and a final result generating unit.

The device contains (Fig. 1) first 1, second 2, third 3 and fourth 4 information inputs, three delay elements 5-7, a block 8 forming an intermediate result, a block 9 forming the final result, the first 10 and second 11 outputs of the result.

The block B for forming the intermediate result and the block 9 for forming the final result are made in the form of one-digit adders, each of which contains four elements AND 12-15, four elements OR 16-19, element NOT 20, first 21 and second 22 information inputs of the single-digit adder , input 23 of transfer of a one-bit adder and outputs 24 and 25, respectively, of transfer and the sum of a one-bit adder

The device works as follows.

Any K-bit normalized number X in the redundant binary number system can be transferred successively from the leading bits to the younger ones on the X and X buses, with each bit Xp of this number of the order being represented by the formulas

in this case it is put in two binary numbers, Chr and ChrG

X i; Xp. (3) P

 R

(BUT)

Where

Xp

;

rd discharge;

the number of the p-th bit is positive; Xp - the number of the p-th number is negative

bit

The coding of the excess bit values can be summarized in Table. one.

Table 1

20

iiir

To add two numbers M x + y in the redundant number system, they are sequentially, starting with the higher bits, to the inputs 1-4 of the device, while at the outputs 10 and 11 in the same sequence from the higher bits to the younger ones, the result bits in the same numbering system. There are two options for connecting operands to a device, listed in Table. 2, while the operation of the device is identical for both cases of connection, therefore the second option is considered further

table 2

M., -2t P., - Wed, - Lv., (2)

3

where Mj, u,%

Urn, Xp, X - binary digits of the op - rand; p is the binary number of the intermediate sum of the p-th bit;

, 1 | - the digit of the transfer in the p-th bit d.

In formulas (1) and (2) the variables

right parts have the same weight,

I

they arrive at the inputs of blocks 8 and 9 Variables Pr., in the left part (1) and left part (2) have double weight, as indicated by factor 2. Elements 5-7 serve to match the weight of the variable with its arrival time at the input of the former. delays. Blocks 8 and 9 serve to perform the algebraic addition of input variables in accordance with formulas (1) and (2).

The inputs 1-4 receive the operands X,, yt, Y, respectively. In blocks 8 and 9, the values of intermediate and final results are calculated at each pth cycle. From the output 25 of the block 8 to the input of the delay element 6, the value of the intermediate sum Cp comes from, output 24 of the same block to the input 23 of the block 9 receives the transfer signal Ex.,, From the outputs of elements 5 and 6, the delays enter the inputs 21 and 22 of the block 9 respectively

signals ur and cd.

I g

After the end of the transient processes in the block 9 circuit, at the p-th clock, the output of the device 10 receives the result value Mj, from output 25, and the result value Mn, from output 24 enters the input of delay element 7, from the output of which output 11 of the device enters value of the result M .. Addition of two

814874

K-bit numbers are performed in (K + 2) work cycles.

Claims (1)

Claims of the invention pj A device for adding s to a redundant binary number system, comprising an intermediate result formation unit, a final result formation unit and three 10 delay elements, with the first, second, third information inputs of the device connected respectively to the first, second, third information inputs of the generation unit 15 of the intermediate result, the first output of which is connected via the first delay element to the first information input of the final result generation unit, the second information input of which through the second delay element is connected to the fourth information input of the device, the second output of the intermediate result generating unit is connected to 25 with the third information input of the final result generating unit, the first output of which is connected to the input of the third delay element, characterized in that 30 in order to simplify the device and increase its speed, the intermediate and final result forming units each contain one one-bit binary adder, the inputs of the first and second operands and the transfer of each of the one-digit binary accumulators being the first, second and third inputs of the corresponding XQ block, and the outputs of the sum and transfer, respectively, the first and second outputs of the corresponding block, the output of the third delay element and the second output of the block forming the final result are outputs 35 45 devices. P 12 YU P G9 kl /five / 7 /five /five / LU g l 2