SU1377821A1 - Device for extending time intervals - Google Patents

Abstract

The invention can be used in automatic control systems and serves to increase the accuracy of the device. The device contains a pulse generator 1, a reversible counter 2, an element OR 3, a divider 4 frequencies, a counting trigger 5, elements AND 6-9 and a element NOT 10. The introduction of the element NOT 11 D-flip-flops 12 and 13 and the formation of new functional connections allows to form a time interval on the falling edge of the input pulses regardless of the duration of the latter. Noise immunity of the device is achieved due to the fact that the beginning and the end of the transformed interval are formed by various elements of the device and does not depend on the response time of the counting trigger 5. 2 Il.

Description

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The invention relates to a pulse and measurement technique and can be used in automatic control systems.

The aim of the invention is to improve the accuracy due to the formation of a time interval on the falling edge of the input pulses regardless of the duration of the input pulses and the increase in noise immunity due to the fact that the beginning and end of the transformed interval are formed by various elements of the device and do not depend on the time of operation of the counting trigger.

FIG. Figure 1 shows the structural electrical circuit of the device for extending time intervals; in fig. 2 - device operation diagrams

The device for extending the time intervals comprises a pulse generator 1, a reversible counter 2, an element OR 3, a divider 4 frequencies, a counting trigger 5, the first, second, third and fourth elements AND 6-9, the first and second elements NOT 10 and 11, the first and second D-triggers 12 and 13, input 14 and output 15 tires.

The input of the counting trigger 5 is connected to the output of the first element AND 6, the first input of which is connected to the input bus 14. The first input (the input of the reversible counter 2 is connected to the output of the second element And 7 to the first input of the fourth element And 9 and through the second element NOT 11 to To the input of the second D-flip-flop 13. The first input of the second element And 7 is connected to the direct output of the counting trigger 5, the inverse output of which is connected to the first input of the third element And 8 HC With the input of the first D-flip-flop 12. The output of the element And 8 connected via a 4 frequency divider to the second at entry (entry subtracting) a reversible counter, the second input of AND 7 soedi1

with the output of the generator 1 pulses of the second input element And 8. Vertical meter 2 is connected

Let the beginning of the temporal transducer act at the beginning. This impulse stuns the input state of the impulse (see the potential of the trigger of 5 impulses gene res. Element And reversible First impulse input of the OR 3 element on 15 devices formed by the back front of the last-stunned state of the mouth (see low potential

by the moves of the D-flip-flops 12, 13 and th-50 element AND 9. The first element is NOT 10 - with the second ohm of the element OR 3. The second input of the input And 6 is connected to the direct output of the trigger-trigger 12 output 55 th D-flip-flop 13. D-inputs trigv 12 and 13 are connected to the minus of the power supply unit.

Pulses from the pon's impulse input divides the element AND 8 from the inverse of trigger 5 (with potential and Gera 12 (see

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The device works as follows.

In the initial position, the countable tri1 is ger 5, the reversible counter 2 is in the zero state, and the triggers 12, 13 are in the single state. The signal from the output of the pulse generator 1 does not pass to the first input of the reversible counter 2, since element 7 is closed at the first input by a low potential from the direct output of the counting trigger 5. The signal from the output of the pulse generator 1 does not pass to the input of the frequency divider .4 as on the third input of the element And 8 there is a low potential from the inverse output of the trigger 12. Element And 6 is open at the second input by a high potential from the direct 20 output of the trigger 12, and the element 9. is open at the second input by a high potential from the direct output of the trigger 13. At the exit e OR 3 (on output line 15 devices) low potential.

Let a pulse enter the input bus 14 of the device, which fixes the beginning of the time interval to be converted (see Fig. 2a). This impulse through the element 6 is fed to the input of the counting trigger 5, which is set to the one state by the falling edge of the input impulse (see Fig. 26, c). The high potential of the direct output of the counting trigger 5 permits the passage of pulses of the generator 1 pulses through the element 7 to the summing input of the reversible counter 2 (see Fig. 2e). The first impulse through the open on the second input element. And 9 and through the element OR 3 enters the output bus 15 of the device (see Fig. 2m), thereby fixing the origin of the pre-g formed output signal. On the falling edge of the first pulse arriving at the C input of the D flip-flop 13, the latter is set to the zero state (see Fig. 2g), closing with a low potential from the direct output

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The pulses from the output of the generator 1 pulses still do not come to the input of the 4 frequency divider, since element 8 is closed by a low potential from the inverse output of the counting trigger 5 (see fig. 2c) and a low potential of the inverted output of trigger 12 (see fig. 2k) .

During the time Tgj (see Fig. 2a), the number of pulses N will be fixed in the reversible counter 2, () ((see Fig.2d) On the falling edge of the second pulse arriving at the input bus 14 of the device (see FIG. 2a) and indicating the end of the converted interval b, the counting trigger 5 is set to the initial (zero) state (see Fig. 26, c). And the low potential of the direct output of the trigger 5 closes the element And 7, the pulses to the summing input of the counter 2 stop, and the high potential from the inverse of the trigger 5 and the trigger 12 opens the element 8. And the pulses from the pulse generator 1 output via the AND gate 8 and the frequency divider 4 begins to flow to the subtracting input of down counter 2 with the repetition rate

f J, where K - the ratio

neither is the 4 frequency divider (see Fig. 2e) These pulses continue to flow until the reversible counter 2 returns to the initial zero state. On the falling edge of the output pulse of the counter 2, the triggers 12-13 are set to the initial (single) state. The low potential from the inverted output of the trigger 12 closes the element E 8, and the pulses from the output of the generator 1 pulses do not reach the input of the 4 frequency divider (see Fig. 2i, k, f, f). The output pulse from the output of the reversible counter 2 through the element NOT 10 and through the element OR 3 enters the output bus 15 of the device (see Fig. 2m), thereby fixing the very end of the converted output signal C d (extended time interval).

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Claims (1)

Claims An apparatus for extending time intervals, comprising a pulse generator, a DLI element, the output of which is connected to the output bus, a frequency divider, a counting trigger, the input of which through the element And is connected to the input bus, is reversible IQ counter, the first input of which is connected to the output of the second element I, the first input of which is connected to the direct output of the counting trigger, the inverse output of the counting trigger is connected to the first input of the third element I, the output of which is connected through the frequency divider to the second input of the reversible counter, the second The input of the second element AND is connected to the output of the pulse generator and to the second input of the third element AND, the fourth element AND, the first element is NOT, characterized in that, in order to increase accuracy and noise immunity, additional A second HE element and two D-flip-flops are introduced, the inverse output of the first D-flip-flop is connected to the third input of the third element I, the output of the reversible counter is connected to the S-inputs of the first and second D-flip-flops and through the first element NOT to the second the input of the OR element, the second input of the first element AND is connected to the direct output of the first D-flip-flop, whose C-input is connected to the inverse output of the counting trigger, the output of the second And element is connected to the first input of the fourth And element, the second input of which is connected to the direct exit the second D-flip-flop, whose C input is through the second element is NOT connected to the output of the second And element, the D inputs of the flip-flops are connected to the minus of the power source. 35 40 I- j 0 uiit rirlо 5 U5i J-1r e // " shi1 11Sh1 ishiii i-i 3 us fl P and .. / f. l w2 M i / f5 cpue 2