SU1374424A1 - Coded converter - Google Patents

Abstract

The invention relates to the field of pulsed technology and can be used in the construction of buffer cascades between multi-valued and binary logic. Code converter (KP) contains input bus (W) 1, total W 4, power inverters 2, 3, 8-10, W 5, 11, 12, output W 6, 7. The invention expands KP functionality by introducing the fourth logical state (level). 1 silt, 1 tab. (L with 4 4 GS 4

Description

The invention relates to a technique in terms of technology and can be used to construct buffer stages between multi-valued and binary logic.

The purpose of the invention is to expand the functionality by introducing a fourth logic state (level).

The drawing shows an electrical circuit diagram of a code converter.

The device contains an input bus 1 connected to the inputs of the first and second inverters 2 and 3, the source of the p-transistor of the second inverter 3 is connected to the common bus 4, the first power supply bus 5. the first output bus 6, the second output bus 7 connected to the output of the second inverter 3, the third inverter 8, the fourth and fifth inverters 9 and 10, the second and third power buses 11 and 12, the inverters are made on CMOS transistors, the input bus 1 is connected to the input of the third inverter 8, the output of which is connected to the source of the fourth transistor inverter 9, the source of the p transistor coupled to an output of the first inverter 2, the source of the n-transistor is connected to the first bus pitaI or 5, with the source p-n transistor to

Inverter 10 and the source of the p-transistor of the second inverter 3, the output of which is connected to the input of the fourth inverter 9, the output of which is connected to the input of the fifth inverter 10, the output of which is connected to the first output bus 6, and the source of the p-transistor to the common bus 4 and with the source of the p-transistor of the third inverter 8, the source of the p-transistor of which is connected to the second power line 11, the source of the p-transistor of the first inverter 2 is connected to the third power line 12.

The device works as follows.

Bus 1 receives a logical signal in the alphabet 0,1,2,3. On tires 6 and 7, an appropriate binary combination is formed. Bus 12 11 and 5 receives the supply voltage forming (corresponding) logical 1, 2, 3. The device operates in accordance with the truth table.

Logical level

20

The dimensions of the p-and n-transistors of the inverter 3 are chosen so that the switching of the inverter 3 occurs

between voltage levels, corresponding to 11 1 1G

AND 2

logical signals

 The dimensions for the inverter 10 are also set.

0

five

0

five

0

five

Similarly, for the inverter 2, the sizes of the transistors are selected to switch the inverter between the logic signals 2

Claims (1)

Invention Formula The code converter containing the input bus connected to the inputs of the first and second inverters, the source of the p-transistor of the second inverter is connected to the common bus, the first power bus, the first output bus, the second output bus connected to the output of the second inverter, the third an inverter, characterized in that, in order to expand its functionality, the fourth and fifth inverters are introduced into it, the second ii third of the power bus, the inverters are made on CMOS transistors, the input bus is connected to the input of the third inverter, the output of which is It is connected to the source of the p-transistor of the fourth inverter, the source of the p-transistor of which is connected to the output of the first inverter, the source of the p-transistor of which is connected to the first power line, to the source of the p-transistor of the second inverter, and the source of the p-transistor of the second inverter connected to the input of the fourth inverter. 313744244 the output of which is connected to the input of the p -tower, the source of the p-transistor of which the inverter, the output of which is connected to the second power bus, is connected to the first output bus, and the source of the p-transistor of the first inverter p-transistor with the common bus and the torus is connected to the third bus by a pitas source of the p r-transistor of the third inni.