SU1368892A1 - Statistical analyser - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to determine the laws of the distribution of random variables with a small number of measurements. The aim of the invention is to improve the accuracy of determining the distribution law with a small number of measurements. The analyzer contains analog-digital converter 1, delay elements 2, 8, 10, trigger 3, element 4, counter 5, memory register 6, comparison element 7, divider 9, registration block 11. The operation of the analyzer is based on the principle of maximum likelihood, according to which the best estimates of the values of the real distribution function are the values corresponding to the maximum values of the beta distribution of the ordered sequence of values of the real distribution function. 1 il. (L

Description

eight

with

Od 00 CX)

with 1C

The invention relates to computing and can be used to determine the laws of the distribution of random variables with a small number of measurements.

The aim of the invention is to understand the accuracy of determining the distribution law with a small number of measurements.

The drawing shows the functional scheme of the statistical analyzer

The analyzer contains analog-to-digital converter 1, delay element 2, trigger 3, element 4, counter 5, memory register 6, comparison element 7, delay element 8, divider 9, delay element 10, and registration unit 11.

Statistical analyzer works as follows.

Before starting work, register 6 is entered (N-1) - the predetermined value of the sample size, reduced

per unit, trigger 3 is set to

A. Digital-to-analog input

the lattice function of the distribution of the following random signal is temporarily at the second input block

digital hysteresis

After the i-ro pulse, the value (i-1) is generated in the counter 5. The signal from the output of counter 5 is fed to the first input of the comparison element 7 and to the input of the divisible divider 9, to the second input of the comparison element 7, and to the input of the divider 9, the value (N-1) from the output of the register 6 is applied. As soon as the signals at the inputs of the comparison element 7 will become equal (this is the case when i N), at its output a signal is set to set counter 5 and trigger 3 to O. This signal is delayed by the second delay element 8 for the time required to complete the division operation in divider 9. Thus, output divider 9 to the first input of block 11 registration consistently, the values - i 1,2, ..., N

the lattice distribution function of the random signal under study. At the same time, the second input of the block 11 recodes

an inverter with 1 X value; (i 1, N) of an extended ordered sample (including the lower boundary of the domain of possible values of a random variable, the ordered realization of a random variable, and the upper boundary

the domain of possible values of a random variable) is converted to a digital code. The conversion of each i-ro value (i 1,2, ..., N) of the sample is completed by forming, at the output of the analog-digital converter 1, a pulse signal arriving at the input of the AND 4 element and, through the delay element 2, at the input of setting 1 of the trigger 3 At the output of the trigger 3, a single code is set, which enters the input of the element And 4. Since the delay time provided by the element 2 exceeds the duration of the control pulse, the signals arriving at the input of the element 4 do not coincide in time and the first pulse of the sequence does not It goes to the output of the element I 4 and to the counting input of the counter 5. The control pulses with the numbers i 2, ..., N from the output of the analog-digital converter 1 are fed to the input of the element I 4, to the other input of which simultaneously receives a single signal from the output trigger 3 and transmitted to the counting input of counter 5, causing a change in its state. As a result, when entering each

X ,, (i 1, N) values delayed by delay element 10 by the time required to compute the corresponding value of the lattice distribution function.

The principle of operation of the statistical analyzer is based on the use of individual provisions of the theory of order statistics. In this case, the lower a and upper b borders of possible values of a random variable X, which, together with the realizations of a random variable, are presented in the form of an extended ordered sample, are known from physical considerations.

X,, t.

-X ,, -X, b

(one)

45

The corresponding values of the real distribution function (X) form a sequence

50

Y, Y2-Y} - (2)

The probability density of the passage of the integral distribution function at the level Y) for the i-th element of the sequence (1) in a series of N elements is characterized by a beta distribution

N

N-t

I.N. (i-O (N-1)

 (1st;), (3)

satisfying, it has a maximum inside at i i 1 function (3)

which for lOoog about L, the condition 1 i-с N, the interval () one

V i-1 ke y - y

 N-1

V

has a conditional maximum at y; 0 and for i N - at the point У „1. In accordance with the maximum likelihood principle, the best (most probable) estimates for the elements of the sequence (2) —the values of the real distribution function — were V

values of y corresponding to

the maximum value of rotary rate (2), i.e.

i-1

density

V

Have

N-1

i 1,2, ..., N.

Claims (1)

Invention Formula A statistical analyzer containing an analog-digital converter, a counter, a divider, a comparison element, a first delay element, a registration unit, an analog-digital converter information input is an information input of the analyzer, the output of the counter is connected to five 0 five the first input of the comparison element and the input of the divisible divider, the output of Yuriy is connected to the first information input of the registration unit, the output of which is the output of the analyzer, characterized in that, in order to improve the accuracy, a trigger is entered into it, the And element, the memory register , two delay elements, the output of the conversion end of the sampling analog-digital converter connected to the first input of the AND element and through the first Delay element to the installation input of 1 trigger, the output of which is connected to the second input of the AND element, the output of which is connected to the counting input of the counter, the output of the memory register is connected to the input of the divider and the second input of the comparison element, the output of which is connected to the installation input O via the second delay element the trigger and the zeroing input of the counter, the information output of the analog-digital converter through the third delay element is connected to the second information input of the registration unit.