SU1368882A1 - Multiplication device - Google Patents

Abstract

The invention relates to computing and can be applied in the development of high-speed arithmetic devices, the control of which is organized by parity. The aim of the invention is to increase the reliability of the results generated in the device by detecting all the errors caused by its single fault. The device contains a block of the formation of partial products and a block of 2 summation, as well as the newly introduced element I 3 and four blocks A-7 of convolution modulo two with corresponding links. With the help of the blocks and connections entered into the device, all errors (single and group) caused by a single fault are detected in it. 4 ill., 1 tabl, |) (L

Description

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The invention relates to computing and can be applied in the development of high-speed arithmetic devices, the control of which is organized by parity.

The purpose of the invention is to increase the reliability of the results generated in the device by detecting all the errors caused by its single failure.

Fig. 1 shows a block diagram of a device for multiplying j in Fig. 2, a functional diagram of a unit for generating partial products for the case of multiplying A-bit numbers in a device; Fig. 3 is a functional block diagram of the summation unit, for the same case; Fig. 4 is a functional diagram of a one-bit binary adder with duplicate transfer used in the summation block.

The device for multiplying (Fig. 1) contains a block 1 of forming partial products, a block 2 summing the element AND 3, a convolution unit A-7 modulo two from first to fourth, respectively, input 8 of multiplicand, input 9 multiplier, input 10 of the first component input 11 second term, input 12 parity multiplicable, input 13 parity multiplier, input 14 evenness of the first term, input 15 evenness of the second term, output 16 of the higher part of the result, output 17 of the lower part of the result, output 18 of the parity older than the result, output 19 of the lower part of the lower part ata device 20 and the output error flag. The first and second inputs of block 1 of forming partial products are connected to inputs 8 and 9 of multiplicand and multiplier, respectively, the output of block 1 of forming partial products is connected to the first input of block 2, the second and third inputs of which are connected to inputs 10 and 11 of the first and second components, respectively , the output of the higher digits of the sum of block 2 summation is connected to the input of the second convolution unit 5 modulo two and is the output 16 of the highest part of the result of the device, the output of the lower digits of the sum of block 2 is summation Inonii with the input of the third unit 6 convolution modulo two and is the output of the unit 17 younger result, the first and second inputs

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element 3 is connected to inputs 12 and 13 of the multiplicity and multiplier parities, respectively; the output of element 3 is connected to the first input of the first convolution unit 4 modulo two; the second and third inputs of which are connected to the inputs 14 and 15 of the parity of the first and second terms respectively , the fourth input of the first modular convolution unit 4 is connected to the output of duplicated transfers of the summation unit 2, the output of the second modular convolution unit 5 is connected to the first input of the fourth modular convolution unit 7 and is the highest parity output 18 the output of the device, the output of the third convolution unit 6 modulo two is connected to the second input of the fourth convolution unit 7 modulo two and is the parity output 19 of the lowest part of the result of the device; the output of the first modulus 4 convolution unit 4 is connected to the third input of the fourth convolution unit 7 modulo two, the output of which is the output 20 of a sign of device error.

Block 1 is designed to form partial products of a multiplicand multiplier factor. It can be implemented as a matrix of two-input elements I. In Fig. 2, for the case of multiplication in a device of 4-bit g factors, such a matrix is shown. It contains sixteen two-input elements And 21-36 with outputs from 37-52, respectively.

In block 2, the summation of partial products formed in block 1 and arriving at the first input of block 2 summation taking into account the weights of their bits is carried out. In addition to partial works in block 2, two more terms are received through its second and third inputs from inputs 10 and 11 of the device. This ensures the implementation in the multiplier of the following complex function:

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F X-YH-A + B

where X, Y, are p-bit multiplicative and multiplier respectively

A, B are the first and second terms, respectively.

Note that the p-bit terms A and B are summarized in block 2 and n

A little bit dammed product XY. This ensures efficient use of the device when using LSIs.

FIG. 3 is a case of a functional block diagram of summation 2, which uses the inputs 53-56,57-60 of the first and second terms and sixteen one-bit binary adders 61-76 with duplicate transfer. The outputs of duplicate transfers of one-bit binary adders 61-76 form the output of 77 duplicate transfers of block 2 of summation. The outputs of the sum of one-bit binary adders 62 and 63 and the outputs of the sum and transfer of a one-bit binary adder 61 form the output of the old digits of the sum of block 2, which is the output 16 of the highest part of the device result, the outputs of the sum of one-bit binary adders 64.65.70 and 75 form the output of the lower bits of the sum of block 2, which is the output 17 of the lower part of the result of the device.

Fig. 4 shows a functional diagram of a one-bit binary adder with duplicate transfer, which can be applied in block 2 of summation. The adder contains the elements And 78-81, the elements SHSh 82-84, the element HE 85 and the element 86 addition modulo two. The circuit of this adder is known and is described by the following logical expressions:

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с „t„ ®с.,.,

with „+ -t„

Tn (Gn +

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Cn,)

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T h

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Bn5n , B, transfer generation function;

transfer function

the sum, the transfer and the duplicate transfer, respectively, the bit terms of the adder,

Using the element And 3 and the first convolution unit 4 modulo two, the output of the latter generates the value of the predicted parity of the result of the device according to d by

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PF P, R ®РД®РЦ © RS

and

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РЬ Р Р 15

20

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parity accordingly

multiplier X and DIMENSION

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parity, respectively, of the first A and second B terms;

the parity of duplicate transfers of block 2 summation,

predictable parity result.

Using the second and third modulo 5 and 6 convolution blocks, the device generates the value of the actual parity of the result, which is compared in the fourth convolution block 7 modulo two with the value of the predicted parity of the result. Based on this comparison, at the output 20 of the device, an error signal is generated or not.

The device works as follows.

After supplying the factors to the inputs 8 and 9 of the device in block 1, partial products are formed, which then go to block 2, where they are summed up taking into account the weights of their bits. At the same time, the summation unit 2 from inputs 10 and 11 of the device is also supplied with two terms, which are added to the younger bits of the product of factors, as a result of which the outputs of the sum of block 2 form a result in a one-bit code, which arrives at outputs 16 and 17 devices. Simultaneously with the execution of the summation in block 2, the duplicate translations arising in it enter the first convolution block 4 modulo two, where they are summed modulo two. The other inputs of this block are given the value of the product of the parities of the factors from the output of the element And 3, as well as the value of the parities of the first and second terms from the inputs 14 and 15 of the device. At the output of the first modular convolution unit 4, an indirectly predicted parity of the result is generated, which is then compared in the fourth convolution unit 7 modulo two with the actual gc parity of the result formed at the outputs of the second and third convolution units 5 and 6. In case of discrepancy between the values of the actual and predicted parities of the result

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At the output of the .0 device, an error signal is generated. If summation unit 2 is constructed using single-digit binary adders with duplicate transfer (FIG. 4), then all errors in its result (single and group) that are caused by a single fault are detected in the multiplier.

Example. Suppose that the output of element 50 and block 1 produces an incorrect result due to the malfunction of element 34. Then this error will necessarily lead to errors in the formation of sums 73.69 and 65, and, consequently, to an error in the discharge of the result with weight. . Let the same fault also cause an error in the formation of transfer of the adder 73, and consequently, in the formation of duplicate transfer from the adder 73 (malfunction of the And 34 element may not cause errors in the formation of transfer of the adder 73). The error in the formation of transfer of adder 73 will necessarily lead to errors in the formation of sums of adders 68 and 64, and consequently, in the discharge of the result with a weight of 2. Thus, the total number of errors in duplicate transfers and in discharge of the result is odd (in the considered in this case, it is equal to three: one error in the duplicate transfer of the adder 73 and two errors in the result bits with weights 2 and 2), which is detected by parity. Similarly, it can be shown that other error classes caused by a single device malfunction will always be detected by parity.

In conclusion, we make an estimate of the number of controlled (blocks 1 and 2) and controlling (blocks 4-7, element 3 and schemes of duplicate transfers of adders 61-76 of block 2) equipment in the device. The results of such a calculation for different sizes of factors in the assumption of using the two-input logical elements AND, OR, as well as the element H are shown in the table.

As follows from the data in the table, the monitoring equipment entered into the device constitutes approximately 55-65% of the amount of the controlled equipment, which confirms the high

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What is the effectiveness of the system control offered in the device?

Claims (1)

Invention Formula A multiplying device containing a partial product forming unit and a summing unit, receiving the first and second inputs of the partial product forming unit, are connected to the multiplicative and multiplier inputs of the device, respectively, the output of the partial product forming unit, the second and third inputs of which are connected to the inputs of the first and second terms of the device, respectively, the output of the higher bits of the sum of the summation block is the output of the higher part of the result the output of the lower bits of the sum of the summation block is the output of the younger part of the result of the device, characterized in that, in order to increase the reliability of the results generated in the device, it contains four convolution blocks Q modulo two and the element I The first and second inputs of the element I are connected to the inputs of the multiplicative and multiplier parities of the device, respectively, and the output of the element I is connected to the first input of the first convolution unit modulo two, the second and third inputs of which are connected to the inputs of the parities of the first and second addends of the device, respectively, the fourth input of the first modulo two convolution blocks are connected to the output of duplicate transfers of the summation block, the output of the higher digits of the sum of the summation block is connected to the input of the second convolution block modulo two, is the output of the parity of the highest part of the result of the device, the output of the lower digits of the sum of the summation block is connected to the input of the third unit of convolution modulo two, the output of which is the output of the evenness of the younger part of the result of the device, the outputs of the second, third, and first convolutional units modulo two are connected respectively with the first, second and third inputs of the fourth convolution unit modulo two, the output of which is the output of a sign of a device error. five 0 five 0 55 57 53 6056 L. 00-9 &/one Gp ci Cn S “