SU1367160A1 - Apparatus for signal transmission with periodic correctioln - Google Patents

Abstract

The invention relates to a technique for transmitting messages based on delta modulation and improves the reliability of the transmitted information. The device contains read 1 block 1, binary modulator 2, integrator 3, rr 4 clock pulses, frequency divider 5, gate 6 block, valves 7–9, el NO 10, frequency multiplier 11, el AND 12,17, 18, e-ti OR 13, RS-triggers 14-16. 1 il.

Description

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with

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one

The invention relates to a technique for transmitting messages based on delta modulation and can be used in communication systems, telemetry and television.

The purpose of the invention is to increase the reliability of the transmitted information.

The drawing shows structures13671602

the third valve 9 short-circuits the output of the integrator 3, and the inputs R of the second and third CG-flip-flops 15 and 16 are respectively signals from the direct and inverse outputs of the first RS-flip-flop 1A. Its inputs S and R are given a signal from the output of the binary modulator 2 , Depending on the. kind of

on the electrical circuit of the proposed Q symbol at its output (1 or o)

Devices. At this moment, the first RS trigger 14

The device contains a subtracting state 1 or O,

block 1, binary modulator 2, integra-So, for example, if the output is binary 3, generator 4 clock pulses1F

owls, frequency divider 5, block 6, the first, second and third valves 7-9, the element NO 10, the frequency multiplier 11, the first element AND 12, the element OR 13, the first, second and third RS-triggers 14 - 16 , the second element And 17, the third element And 18.

A device for transmitting signals with periodic correction operates as follows.

20

modulator 2 1, the trigger 14 enters the state. If at this moment there is a signal at the output of the gating unit 6, the second element I 17 is opened and from its output 1 is fed to the input S of the third RS flip-flop 15, R of which is fed from the inverse output of the first trigger 14. Thus, the third trigger 15 is transferred to state 1. The high level from its output is fed

1602

the third valve 9 short-circuits the output of the integrator 3, and the inputs R of the second and third CG-flip-flops 15 and 16 are respectively signals from the direct and inverse outputs of the first RS-flip-flop 1A. Its inputs S and R are given a signal from the output of the binary modulator 2 , Depending on the. kind of

So, for example, if the output is binary

modulator 2 1, the trigger 14 enters the state. If at this moment there is a signal at the output of the gating unit 6, the second element I 17 is opened and from its output 1 is fed to the input S of the third RS flip-flop 15, R of which is fed from the inverse output of the first trigger 14. Thus, the third trigger 15 is transferred to state 1. The high level from its output is fed

The input signal is fed to the first25 at the input of the OR element 13, from the output of the first valve 7, from the output of which the signal goes to the blocking signal, goes to the first input of the NO element 10 and to the second input of the reading unit I, the input of the first element And 12. So

With binary modulator 2. In subtractive unit 1, a difference signal between the input signal and the approximation signal produced by integrator 3 is formed. The difference signal enters binary modulator 2, where, in accordance with the sign of this signal, a sequence of pulses 1 is formed and O, carrying information about the input signal increments at clock points. The sequence of these pulses goes to the communication channel and to the input of the integrator 3.

From the output of the frequency divider 5 to the input of the gating unit 6, short pulses are sent, the period of which corresponds to the periodicity of the correction process. Gating unit 6 produces a short-term control voltage supplied simultaneously to the first inputs of the second and third elements 17 and 18 and to parallel-connected second inputs of valves 7–9. The first valve 7 removes the input signal from the subtracting unit when the control voltage is applied. 1, and the second valve 8 bridges this input, thus providing a zero signal to the input of the subtracting unit 1. At the same time

element 10 NO disables output

generator 4 from binary modulator 2, stopping the formation of a delta flow at the main frequency, and the first element I 12 provides the clock signal from the output of the multiplier 11 frequency to the military modulator 2.

When removing the control pulse of gating unit 6, an input signal is supplied to the input of the subtractive-block 1 through the valve 7, the second and three valves 8 and 9 break the corresponding short-circuit circuits and a sequence of 111 type symbols is generated at the output of the binary modulator 2

following in excess of n times the fundamental frequency. The resulting sequence corresponds to a positive voltage jump of the input signal and tends to the true value.

functions at the time of correction.

The process of forming a sequence of the form 111 ... with an increased frequency continues until the input signal level

excels approximating. This moment in time corresponds to the appearance in sequence at the output of the binary modulator 2 O characters. It translates the first RS flip-flop 14 into

3

 the state o, in which the second level of the second element AND 17 is removed from a high level, the third RS-flip-flop 15 goes to the state O, from the output of the element OR 13 O enters the second input of the first element And 12 and unlocks the element NO 10, which results to feed 2-clock pulses to the binary modulator with the fundamental frequency.

If at the moment when the signal from the output of gating unit 6 is output at the output of the binary modulator, o is present, the first RS flip-flop 14, which is in the o state, opens the third element AND 18, the second RS flip-flop 16 goes to state 1. From the output of the element OR 13 1 enters the inhibitory input of the element NO 10 and the second input of the first element AND 12, The binary modulator 2 receives clock pulses with an increased frequency n times, and at its output a sequence of symbols of the type LLC,. as long as the level of the approximating signal is not novits below the input, which corresponds to the appearance of a binary modulator 2 characters 1 in the sequence of characters on the code of the code. This symbol translates the first RS flip-flop 14 into state 1, while the second level of the third element 18 is removed from the second input and the second RS flip-flop 15 goes to the state o, This leads to the return of the device to the original mode of operation with the main clock frequency,

The process of restoring messages to. The receiving side, as with conventional delta modulation, consists in summing stepwise voltages of the same amplitude, taking into account their polarity, depending on the type of symbols of the received sequence.

Claims (1)

Invention Formula A device for transmitting signals with periodic correction, containing series-connected VUVNIIPI Order 6850/55 Circulation 928 Random polygons pr-tie, Uzhgorod, st. Project, 4 671604 reading unit, binary modulator and integrator, as well as the first, second and third valves, the first RS flip-flop, the first AND element and the NO element, the frequency multiplier and serially connected clock generator, frequency divider, gating unit, the output of which is connected to the control The first inputs of the first, second, and third valves, the output of the first valve connected to the first input of the subtraction unit and to the input of the second valve whose output is connected to 15 second input of the subtracting unit, the third input of which is combined with the input of the third valve and connected to the output of the integrator, the reset input of which is connected to the output of the third 20 valve, the second output of the clock generator is connected to the first input of the element NO, and the third output of the clock generator is connected through the multiplier with the first input 25 of the first And element, the outputs of the NO elements and the first And element are combined and connected to the clock input of the binary modulator, the output of which is connected to the inverted reset input of the first RS flip-flop and is the device output, and the information input of the first fan is the input of the device characterized in that, in order to increase the reliability of the transmitted information, the second and third elements AND, the second and third RS-triggers and the OR element are introduced, and the output of the binary modulator is connected to the installation input 40 of the first RS flip-flop, the direct output of which is connected to the first input. the second element And to the reset input of the second RS-flip-flop, the inverse output of the first RS-flip-flop is connected to the 4g the input of the third element And with the reset input of the third RS flip-flop, the second output of the gating unit is connected to the second inputs of the second and third elements And, the outputs of which go are respectively connected to the set inputs of the third and second RS flip-flops, the outputs of which are connected via the OR element to the second inputs of the NO and I. elements Subscription