SU1365133A1 - Memory conserving information in case of power supply disconnection - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices, and can be used in digital information processing systems as an operative or semi-permanent memory with

Description

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back-up from the backup power source when the mains supply is disconnected. The aim of the invention is to increase the reliability of the device. The device contains a drive 1, a block 2 interface, a trigger 3, three elements AND 4-6, elements HE 7, 8, load elements 9, 10, a backup power source 11, keys 12, 14, 17, the first 13 and second 15 threshold blocks, block 16, powering off the main power supply, switching-on element 18 of the backup power source, cumulative element 19. Improving the reliability of the device is achieved by blocking access to drive 1 by the block 16 at the time of changing, disconnecting or restoring the main power supply, and drive 1 is switched to Power supply from backup power source 11, while limiting the current consumed from backup source 11 at the time of disconnecting the main power, and leakage currents through the elements NOT 7, 8 in steady state when powered from backup source 11. 1Cp. f-ly, 4 ill.

The invention relates to computing, in particular, to storage devices, and can be used in digital information processing systems as an operative or semi-permanent memory with water from a backup power source when the power supply is disconnected.

The aim of the invention is to increase the reliability of the device.

Figure 1 shows the functional diagram of the device and the schematic diagrams of the main power supply disconnecting unit and the third key; Fig. 2 is a functional diagram of the most preferred embodiment of the interface block; on fig.Z-schematic diagrams of the first key and the first threshold unit; figure 4 - schematic diagrams of the second key and the second threshold unit.

The device contains (-Figger 1, block 2 of the interface, trigger 3, the first to the third elements AND 4-6, the first 7 and the second B elements NOT the first AND 9, the second 10 load elements, the backup power source 11, the first key 12, first threshold unit 13, second key 14, second threshold unit 15, block 16 for powering off the main power supply 2, third key 17, switching on element 18 of the backup power source, storage element 19, input 20 and output 21 of the main power source of the device 22 initial settings, input 23 of recording mode, input 24 of mode Th nor, address inputs 25, informational inputs-outputs of the device 26, a signal conditioner 27. Block 16 of the main power supply of the storage device contains (FIG. 1) a key transistor 28, control transistors 29-31 first to third and resistors 32-35 from first on the fourth. The third key 17 contains the key transistor 36 and the resistor 37. The device also contains the output 38 of the identification of the device state.

The interface unit 2 contains (FIG. 2) a signal driver 39, a decoder 40, address shapers 41, two directional transceivers 42 and an OR element 43, as well as the first 44 and second 45 outputs, the first 46 and the second 47 groups of outputs 2 wives

The first key 12 contains (fig.Z) key transistor 48 and the limiting resistor 49.

The first threshold unit 13 includes output transistors 50 and 51, control transistors 52-55, diodes 56-60, capacitors 61 and 62, and resistors 63-73.

The second switch 14 comprises (FIG. 4) transistors 74 and resistors 75 and 76.

The second threshold unit 15 contains transistors 77 and 78, diodes 79-81, capacitors 82 and 83, and resistors 84-87.

5 The device works as follows.

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The voltage of the main power supply is fed through the input 20 and the output 21 (Fig. 1) to the input of the key 12 and the first input of the block 13.

During the time required to complete all transients, unit 13 keeps the input of key 12 in a high-resistance state, which leads to blocking of key 12, and at the second output of unit 13 a inhibitory potential, a logical zero, is formed. Then from the output of block 13 the resolving potential is fed to the input of the key 12.

In this case, the key switches the input 20 to the input of the key 12. Thus, the supply voltage is supplied to the block 2, the driver 27, the elements AND 4, 5, 6 and the elements NOT 7, 8, the block 15, the first input of the block 16 and the input of the key 17 The trigger 3 is set by a signal from the output of the former 27 to a fixed state, in which its output forms a logic zero level, which is fed to the input of the AND 6 element, from the output of which the logical zero is fed to the inputs of the AND 4, 5 elements and to the output 38 devices. Thus, the passage of signals from the outputs 44 and 45 of block 2 to the inputs of the mode and the sample of accumulator 1 is blocked. At the second output of block 13, a resolving potential is formed - a logical unit. When the supply voltage is applied to the first input of the block 16, the transistors 31, 29 and 28 are unlocked. The voltage of the main power source comes from the output, the block 16 to the power supply input of the drive 1. At the same time, the switch 17 of the key 17 is unlocked by connecting the output 21 of the main power supply to the power supply output of the accumulator 1. When a signal is set to the input 22, the flip-flop 3 switches. In this case, the potential of the logical unit from the output of the trigger 3 is fed to the input of the element AND 6, at the other input of which there is a logical unit. The potential of the logical unit from the output of the element And 6 is fed to the inputs of the elements And 4, 5 and to the output 38, which identifies the access permission to the drive 1.

When writing information to the drive 1, an address code is supplied to inputs 25, and a code of the number being written is input to inputs 26, and a write pulse is input to input 22. In this case, the output 44 of the block 2 forms

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There is a positive polarity impulse that enters the input of the AND 4 element, since in the access mode to storage 1, another potential of the AND 4 element has the potential of a logical unit that enters the input of the NO 7 element, from which the negative polarity impulse arrives to the input of drive mode 1. Drive 1 is then set to the recording mode. The sampling signal of the accumulator 1 output 45 of block 2 through the element And 5, the element NOT 8 is fed to the input of the sample of accumulator 1 also by the level of logical zero, which allows the recording of information into the accumulator 1.

The write cycle ends at the falling edge of the write pulse. At the same time, at the outputs 44 and 45 of block 2, the levels of logical zero are set and, accordingly, at the inputs of the mode and the accessory of accumulator 1 — the levels of the logical unit that provide the information storage mode. In case of a match, an address code is fed to input 25, and a read pulse is fed to input 24. In this case, the output state 44 does not change, therefore, at the input of drive mode 1 there will be a logical unit level and drive 1 will be set to read mode. The address code from the outputs 47 of block 2 goes to the address inputs of accumulator 1, the sampling input of which from the output of element 8 does not receive a sampling signal, generated at output 45 of block 2. The read information from information output of accumulator 1 passes through block 2 to outputs 26. The change in the main supply voltage at input 20, i.e. its short-term increase or decrease as a result of a power failure or shutdown of the main power supply triggers blocks 13 and 15.

From the output of block 13 is fed to the first input of the element And 6 prohibiting potential - the level of logical zero, which is fed to the inputs of the element AND 4 and element 5, respectively, blocking the damping of the signals from outputs 44 and 45 of block 2 to the inputs of drive 1. At the same time, from the outputs elements 4 and 5 are fed to the inputs of elements 7 and 8, respectively, the potentials of a logical zero, and from the outputs of elements 7 and 8, the levels of logical units come to the inputs of the mode and

reversing the accumulator 1, providing information storage mode in the accumulator 1. At the same time, the block 13 blocks the key 12, and the output ac of the block 15 enters the input of the key 14 allowing the switching potential. In this case, the key 12 is opened, breaking the circuit between its output and the input 20, and the key 14 is closed, connecting the output circuit of the key 12 to the output 21.

Thus, the voltage is removed from the power inputs of block 2 of driver 27, flip-flop 3, elements AND 4-6, elements NOT 7, 8 from the first input of block 16 and the input of key 17. At the time of removing the main voltage from the power inputs of elements NOT 7 and 8 at their outputs, the potential of the logical unit is stably maintained, since, first, until the voltage of the main power supply is removed, the inputs of the HE elements 7 and 8 have the potential of a logical zero, and n; their outputs - the potential of a logical unit; secondly, the reduction of voltage from inputs pi

NOT 7 elements are realized by closing them into soda and power outputs between each other with a key 14, thirdly, the potential of a logical unit is retained by applying voltage across load elements 9 and 10 from the power input of accumulator 1. De-energizing the main voltage power from the first input of the block 16 leads to the locking of the transistors 28, 29,31. At the same time, transistor 36 of key 17 is locked. In this case, block 16 breaks the connection between the power input of accumulator 1 and the output of key 12 and, respectively, between the power inputs of block 2, driver 27, trigger 3, elements 4-6, elements 7 and 8. Key 17 breaks the connection between the power output of accumulator 1 and output 21 and, accordingly, the power outputs of block 2, driver 27, elements 4-8.

L 1 is due to the accumulated gQ device automatically transfer charge element 19. Reduction to power from the main source for the voltage at the power input accumulate by unlocking the key 12. However, l 1 leads to unlocking element 18 access to drive 1 by a blocker flowing through the circuit: the output is rewired, because trigger 3 when applying

its voltage to the power inputs of the driver 27 is set to the state in which the level of logical zero from the output of the element 6 and the input 6, the logical zero of the external power source 11, ter - the base of the transistor element 18, the input and output power of the drive 1 and the input source 11. The collector current of the transistor element 18 is supplied to

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the input of the block 16 and through the resistor 33 on the transition base - emitter of the transistor 30.

The magnitude of the collector current of the element 18 may be insignificant, which is achieved by an appropriate selection of the value of the resistor 33, since the transistor 30 is also unlocked with a small current flowing into its base of the charger, because the collector circuit of the transistor 30 is high-resistance, formed by the transition emitter-collector of the locked transistor 31. Transistor 30 is unlocked, and from its

15, the collector output receives a blocking potential at the base of the transistor 29, the latter is locked, which is equivalent to breaking the basic transis-circuit. of the torus 28. Thereby it is prevented

20 inverse mode of operation of the transistor 28. Thus, the block 16 reliably blocks the passage of potential from the power input of the drive 1 to the output of the key 12 and respectively to the inputs

25 of the power supply unit 2, the imaging unit 27, the AND 4-6 elements, the HE elements 7 and 8. The storage unit 1 switches to the information storage mode with water from the power source 11. Lack of level

The 3Q logical unit at output 38 identifies the blocking state of access to drive 1. Storage mode of drive 1 is provided by the presence of levels of logical units at its mode inputs and access by supplying voltage through load cells 9 and 10. Moreover, leakage currents through internal resistances of HE elements 7, 8 are significantly limited, since the input and output of the power supply of the accumulator 1 in the operating mode from source 11 are separated from the power supply circuit of the HE elements 7 and 8, of the AND 4-6 elements of the block 2.

40

If the transfer of accumulator 1 to the operation mode from source 11 occurred due to the main power failure, then after the time required to discharge the capacitor 62 (FIG. 3),

during which blocks the passage of signals through the elements And 4 and 5.

Thus, after the main power fails, blocking access to drive 1 prevents false information from being written to it from external devices.

The absence of a logical unit level at the output of the device 38 identifies the blocking of access to the drive 1.

Claims (2)

Invention Formula 1, A storage device with preservation of information when the power is turned off, containing a drive, a first threshold unit, a interface unit, a storage element, the first and second elements AND, the first and second control inputs of the interface unit being respectively a recording mode input and the input mode of the device reading, the address inputs and information input-output devices of the device are respectively the address inputs and one of the information input-outputs of the interface unit, the first output of which is connected to the first In the course of the first element I, the other information inputs and the first group of outputs of the interface block are connected respectively to the information outputs and inputs of the accumulator, the pi input - the third input of which is connected to the output of which is connected to the first output of the accumulative element; , in order to increase the reliability of the device, the second threshold block is entered into it, from the first to the third keys, the main power storage unit disconnecting unit, the switch-on element of the backup power-1, trigger, form the house of the third key, the second output of the storage element, the power supply output of the storage unit, the fourth input of the power supply disconnection unit and the second input of the third key are connected to the first output of the second threshold element, the second output of which is connected to the second input of the second key, the power outputs of the first and power point, signals, the third element AND, the first 45 elements of the NOT, the elements AND with the first and the third load elements, the first to the third, the sigpher and the second elements, are NOT, the first inputs of the first key and the first threshold block are the input of the main power source, the first output of the first threshold block is connected to the second input of the first key, the output of which is connected to the first inputs of the second and third keys, the input of the second threshold unit, the first input of the main power storage unit disconnection unit, to the input power supply of the AND elements from the first to the third and the first and second elements NOT, the input 0 five 0 5 0 power supply of the interface unit, the power supply input of the signal conditioner and the second input of the first threshold unit, the second output of which is connected to the first input of the third And element, the second input of which is connected to the output of the trigger, the installation input to O of which is connected to the outputs of the signalformer, the third element And connected to the first input of the second element And the second input of the first element And, the output of which is connected to the input of the first element NOT, the output of which is connected to the first output of the second load element and the control input They use the write-read drive storage mode, the sampling input of which and the first output of the first load element are connected to the output of the second element NOT, the input of which is connected to the output of the second element I, the second input of which is connected to the second output of the interface block, the second group of outputs of which is connected to address the inputs of the accumulator, the power input of which is connected to the second terminals of the first and second load cells, the first output of the power supply disconnecting unit and the control input of the switch-on element power supply, the output of which is connected to the second input of the power supply disconnecting unit of the storage device. 0 the house of the third key, the second output of the storage element, the power supply output of the storage unit, the fourth input of the power supply disconnection unit and the second input of the third key are connected to the first output of the second threshold element, the second output of which is connected to the second input of the second key, the power outputs of the first and of the mains, the interface unit and the outputs of the second key, the first and second threshold units are the output of the main power source of the device, the installation input into 1 flip-flop and the output of the third And element are respectively the input of the initial installation and the output of the identification of the device state The power supply and power supply output of the storage device are respectively the input and output of the backup power source of the device. 2. The device according to claim 1, 1 and 2, so that the power supply disconnecting unit of the storage device contains a key transistor, first to third control transistors and first to fourth resistors, and the base of the key transistor connected to the first output of the first resistor, the second output of which is connected to the collector of the first control transistor, the base of which is connected to the collector of the second control transistor and the first output of the third resistor, the second output of which is connected to the collector of the third control transistor, emitter Fi1.g which is connected to the emitter of the key transistor and is the first input of the block, the output of which is the collector of the key transistor, the base of the second control transistor is connected to the first output of the second resistor, the second output of which is the second input of the block, the emitters of the first and second control transistors are combined and are the third input of the block, the base of the third control transistor is connected to the first terminal of the fourth resistor, the torus, the second terminal of which is the fourth input of the block. .S M Ef t | s -L