SU1427518A2 - Electronic circuit - Google Patents

Abstract

The invention relates to electrical engineering and can be used to regulate the power supply of electronic devices capable of shutting it down. The purpose of the invention is to increase speed by speeding up the process of preparation for work due to additional impulses of increased voltage. A second additional power supply key 21, a second key element 22, the switching input of which is connected to the control input of the key 21, a NOT 24 element connected by the input to the control inputs of the key element 22 and the device, and an output to the control input of the first key element 9, the second and third valve elements 27, 28 of the second accumulative element 29. The speed is increased by ensuring the accumulation of energy by the first accumulative element 18 from the high voltage source - voltage source supply voltage plus the voltage boost element 29. 4 pcs. (L with

Description

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The invention relates to electrical engineering, in particular, to adjustable sources of secondary power supply of semiconductor constant-power units with an output arranged in phip open collector. The aim of the invention is to improve the speed by speeding up the process of preparation for work due to additional pulses of increase ;. cervical tension in

Fig. 1 shows a block diagram of an electronic device; FIGS. 2-4 are electric circuit diagrams of a power supply key of a group, an additional power key and a key element, respectively,

; The device (Fig. 1) contains the address decoder 1, the inputs 2 of which are in- | 1 the most significant bits of the address inputs, the keys of the 3.1-SN power supply of the first control inputs 4. 4. The OUT of which are connected to the -group of the outputs of the decoder 1 addresses, modules 5.1-5. The memory of the group of power inputs of which are connected to the outputs. N corresponds to the key box ZZ-Z.Sh of the power supply of the first five additional power switch 7, the power input of which is connected to the output B for connecting the power source , first key element 9, in the power supply of which is connected to the bus Z of zero potential, and the switching input 11 is connected to the control input of the first auxiliary power supply key 7, load elements S I2.JI the first 13 and the second 14 block decoupling elements, the first terminals of which are combined and connected to the switching To the input 11 of the first key element 9, the second outputs of the loads. The elements 12 are connected respectively to the single-out outputs of the 5.1 modules 5.N group memory and the numeric outputs 15 of the device the second terminals of the first block 13 isolating elements Dinen with outputs, N of the corresponding power supply keys 3Л-3,11 of the power supply group, the second control inputs lbL-lb.N of which are connected respectively to the second pins of the second block 14 isolation elements, the first valve element 17 and the first accumulation element 18 which are connected sequentially between b and comms

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ru10111; it has the input 19 of the first additional key 7 of the power supply, the power inputs of the keys ZL-Z.K electro. the power supply is connected to the common output 20 of the first valve element 1 7 and the first accumulation element 1B, the second additional power supply switch 21, the power supply of which is connected to the output 8, the second key element 22, the power supply of which is connected to the bus 10 of zero potential, and the switching input 23 connected to the control input of the second auxiliary power supply key 21, the element NOT 24, the input of which is connected to the control input of the second element 22 and the control input 25, and the output connected to the control at the input 26 of the first key element 9, the second valve element 27, the third valve element 28 and the second storage element 29s with the second 27 valve and second 29 storage elements connected in series between the output B and the switching input 30 of the secondary power supply key 21, and the third valve element 28 is connected between the common terminal 20 of the first 17 valve and the first 18 accumulative elements and around it the output of the second 27 valve and the second 29 accumulative elements.

The address decoder 1 can have a strobe input. The modules 5.1-5L1 of the memory of the group can have strobe inputs that are connected respectively to the output group 4. of the decoder. one . Each key 3.1-3.N of the power supply group (Fig. 2) contains an open collector logic element 32, a reference voltage source 33 (zener diode), transistors 34 and 35, and resistors 36-38. Resistors 36 and 38 are connected between the power supply terminal 20 and the base and the emitter of the transistor 34, respectively, and the resistor 37 between the latter collector and the zero potential bus. The source 33 of the reference voltage is connected in parallel to the resistor 37. The base of the transistor 34 is connected to the output of the element 32, the input of which is the first control input 4.I-4, N. The base of transistor 35 is connected to the collector of transistor 34 and is the second control input 16L-16.1,

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The collector of the transistor 35 is connected to the power supply 20, and the emittance, ter - to output 6, I-6, N of the key 3.1-3.N. Logic element 32 with an open collector can be implemented on two series-connected elements: an integral element is NOT a normal type and an integral element is NOT with a high-voltage code.

Additional switch 7 (21) of the power supply (FIG. 3) contains a transistor 39, diodes 40 and 41, and resistors 42 and 43. The first outputs of resistors 42 and

43. connected and connected to the base of the transistor 39 and the anode of the diode-40. The second output of the resistor 42 is connected to the zero potential bus 10. The collector of the transistor 39 is connected to the second terminal of the resistor 43 and to the terminal 8. The switching input 19 (29) of the auxiliary power supply switch 7 (21) is connected to the emitter of the transistor 39

and the anode of the diode 41. The cathode of the latter is connected to the cathode of the .40 diode and step II (23).

The key element 9 (22) contains a logic element 44 with an open collector, a transistor 45 and a resistor 46. The input with the output 26 (25) of the element

44 is a control input, and the output through a resistor 46 is connected to the input of a +5 V supply voltage source (not shown in Fig. 1) and the base of transistor 45, the emitter of which is connected to the zero potential bus 10, and the collector is a switching input 11 (23) key elements

9 (22).

The electronic device operates as follows.

Selection of information from the 5.1-5.N modules of the memory of the group is carried out in cycles, the duration of which can be constant or variable and is determined by the specified access mode (synchronous or asynchronous).

In each circulation cycle, the device operates in two basic modes: Operation and Standby, regardless of the cycle duration in order to save energy

Tr Trmc const, where Tr. "Cz - the minimum duration of the mode of Operation, is sufficient to reliably retrieve information from the modules 5.1-5.N memory, I, Io. where To.m.n is the minimum waiting time (preparation for work).

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The device is powered, from a stabilized source of direct current voltage V. The bus 10 of the zero potential of the device is grounded. In the initial state (Standby mode at TO TO, min), a single signal is set at the control input 25 of the device (high level). At the same time, the first key element 9 is set to the Standby mode under the action of a zero signal (low level) on its control input 26 from the output of the NOT 24 element. In the Expect mode, the first key element 9 is open. As a result, the control input 11 of the first additional power key 7 is shorted through the first key element 9 to the zero potential bus 10 and the key 7 is also set to the Idle mode. In the Idle mode, I switch. A key 19 input 7 is connected to its control input 1i. The open state of the key element 1I is accompanied by the replenishment of the energy of the first storage element 18 from the power supply source (pin 8). Podzar d element 18 wasp. The following circuit exists: pin 8, first valve element 17, accumulator element 1B, switch 7, key element 9, bus 10 of zero potential. At the same time, at the power supply inputs 20, the keys of the 3rd group maintain a voltage of approximately + 4.3 V, equal to the difference in voltages at step 8 and voltage drop at the first valve element 17. In addition, the open state of the first closure element 9 ensures low - impedance state of the first inputs of load elements (modules 5.H) and junction elements of blocks 13 and 14. As a result, a low impedance state of the second control inputs I6.1-16.N and outputs 6.1-6.N of keys 3.1 is provided -3.N power supplies - groups de-energized sos .N of modules of the memory group, and outputs the numeric unit 15 - standartnyy- level log) cal Q. cop second key 22 under the action of a single signal at its control input 25 set to the operation mode. In the mode of operation, the key element 22 is closed and its commuting.

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consequently, the control input 23 of the second additional 2G power key is in a high-impedance state. As a result, the key 21 is also a power supply. It is installed in the Work mode, in which its switching input 30 is connected to the output.

4y 8 ,; However, the current in the circuit of the switching output 30 of the power supply switch 21 fails. The second cumulative element is 29 times. On the common output of the second valve 27 and second on 1 optional 29 elements, a potential (+ 4.3 V) is installed, close to the voltage at output 8, at which the current of Cerez is the third valve element 28 "None.

I Decoder 1 can have a gating input input 31. In this case, if there is no 4TV signal, all outputs of the decoder 1 will have single signals, at which, 3.1-3.N power of the group will be set on inputs 4.1- 4, N f standby mode. ;. The decoder 1 may not be built. In this case, one of its outputs will be set to zero, in accordance with the H.D. address code installed on address inputs 2, under the action of which the corresponding power supply key 3il-3-.N will be in Prepare mode.

When retrieving information from the 5.1-5-.N memory modules of the group by address inputs 2, the decoder 1 receives the code of the upper-order address bits, which prepares one of the modules 5..I of the memory for information on the numerical outputs 15 of the device 5. For example, 5.2, via the gate input A.2 and to the voltage pulse to the memory module, the corresponding power key 3.2 via the first control input 4.2. At the same time, the control input 25 of the device receives a zero signal with a duration of Tr, for the duration of which the device switches to Run mode. At the same time, the first 9 and second 22 key elements almost simultaneously switch to the opposite state, respectively, Work and Waiting and, in turn, initiate switching to the appropriate modes: the first 7 and the second

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21 additional power keys,

Switching the key 7 to the Operation mode, its switching input 19 is connected to output 8. As a result, the first accumulation element 18, precharged in the Wait for the previous access cycle to the device, is connected in series and according to the power source and the power inputs 20 of the keys 3.1 -3, N power supply voltage appears approximately equal to +7 V. At the same time, a high impedance state is established at the switching input 11 of the key element 9, providing a high impedance the state of the decoupling elements of the blocks 13 and 14, and consequently, the high-impedance state of the second control inputs 16 and the outputs 6.1-6. The keys of the 3.i-3.N power supply of the group. The key 3.2, prepared for switching on with a zero signal at its first control input 4.2, switches to Run with the second control input 16.2 with a minimum delay and sends a powerful pulse of voltage +5 to the power supply 6.2 at power supply 6.2. At a given duration (Tp) for the Operation mode, the other keys 3.1, 3.3-Z.N remain in the Waiting state under the action of single signals at their inputs.4.1, 4.3-4.N and practically do not consume energy . At the same time, an additional impulse of power supply with a voltage of approximately 5.6 V- appears for the circuit of the second control input 16.2 of the key 3.2, which is fed to their first outputs via the corresponding decoupling element of the block 14. The read information goes to the outputs 15 devices

With the switching of the second auxiliary power supply key 2.1 to the Standby mode, its switching input 30 is connected via the second key element 22 to the potential potential bus 10. As a result, the second cumulative element 29 is charged from the power supply (step 8) to form the boost voltage in the Standby mode of the current device access cycle. Charge chain of storage element

29 form: pin 8, the second valve 27 and the second cumulative 29 elements, a key 21, a key element 22, a tire 10 of zero potential.

When the zero signal e of the input 25 is removed, the device switches to the Standby mode. The first 9 and second 22 key elements almost simultaneously switch to opposite states of the Wait and Work, respectively, and, in turn, initiate the switch to the corresponding modes of the first 7 and second 21 additional keys, power supply.

The switching of the first key element 9 into the Standby mode is accompanied by the simultaneous discharge of the capacitive components of the device’s numerical outputs 15 through the load elements 12, output 6.2 and the input 16.2 of the key 3.2 through the corresponding isolating elements of blocks 13 and 14 on

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a storage element 1B, a first additional power switch 7, a first key element 9, a tire 10 of zero potential. As the energy from the second storage element 29 is transferred to the first storage element 18, the voltage at the common output of the second valve 27 and the secondary storage battery 29 decreases, the current through the third power element 28 stops and the second additional power switch 21 automatically shuts off. With

15 this is the readiness of the first storage element 18 for the next circulation cycle (for To To. Mic, it is maintained by replenishing its energy along the main charge circuit: 8

20 cumulative element 18, the first additional key 7, the first key element 9, the bus 10 of zero potential, With the cessation of current through the third valve element 28 (through the aerial 10 of zero potential, accelerating 25 times To.cm) can be immediately

thus, the process of resetting the power supply 6.2 and the digital outputs 15 connected to the memory module 5.2,

With the switching of the first additional key 7 to the Standby mode, its switching input 19 connects via the first key element 9 to the zero potential bus 10,

By switching the second auxiliary key 21 to the Operation mode, its switching input 30 is disconnected from the zero potential bus 10 and connected to the output 8. As a result, the second accumulation element 29, precharged at the Operation stage, actually connects to the device in series and is connected in series with power supply. At the total output of the second valve 27 and the second storage element 29, an impulse of bias voltage with an amplitude of approximately +7 V appears,

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the next call was made to the device.

The decoder 1 converts the address code of the highest times of the device to a unitary code to provide preparation (permission) for switching on one of the 3.1-3.N keys of the power supply.

The keys 3.1–3, N of the power supply group (FIG. 2) operate as follows.

In each cycle of accessing the device, the 3.1–3.N power supply key sequentially switches to one of three states: Preparation, Operation, Standby, determined by the combination of signal levels at its control inputs 4,1-A, N and 16 , 1-1b, K.

In the initial state - Mode - waiting for input 20 of power supply

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3.1-3.N is supplied with a voltage of approximately +4.3 V, input 4.1-4, N is a single signal, and

under the action of which the first accumulator CQ at input 16.1-16, N is a zero signal.

the tel-element 18 is forced and the output of the element 32 is set

flax in a high-impedance state; transistors 34 and 35 o are closed, for example, briefly (for a given

Tv.shts) is charged on an additional charge circuit. An additional charge circuit of the first accumulative gg element 18 is formed: vysod 8, a second additional power switch 21, a second accumulator element 29, a third valve element 28, the first

output output 6.1-6.N key 1.3-3. it is absent and it consumes almost no energy.

When accessing the device on the input 4.1-4.N of the key 3.1-3, N, a zero signal is applied, under the action of which

a storage element 1B, a first additional power switch 7, a first key element 9, a tire 10 of zero potential. As the energy from the second storage element 29 is transferred to the first storage element 18, the voltage at the common output of the second valve 27 and the storage battery 29 decreases, the current through the third portable element 28 stops and the second additional power switch 21 automatically turns off . With

Thereby, the readiness of the first storage element 18 to the next circulation cycle (for To To. Mic, is maintained by replenishing its energy along the main charge circuit:

accumulation element 18, the first additional key 7, the first key element 9, the tire 10 of zero potential, With the cessation of current through the third valve element 28 (through the given 35

the next call was made to the device.

The decoder 1 converts the address code of the highest times of the device to a unitary code to provide preparation (permission) for switching on one of the 3.1-3.N keys of the power supply.

The keys 3.1–3, N of the power supply group (FIG. 2) operate as follows.

In each cycle of accessing the device, the 3.1-3.N power supply key sequentially switches to one of three states: Preparation, Operation, Standby, determined by the combination of signal levels at its control inputs 4,1-A, N and 16, 1-1b, K.

In the initial state - Mode - waiting for input 20 of power supply

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The output at the 6.1-6.N output of the 1.3-3.N key is absent and it consumes almost no energy.

When accessing the device at the input 4.1-4.N of the key 3.1-3, N, a zero signal is applied, under the action of which

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it enters the Prepare state, the output of element 32 is set to a low impedance state, with the result that transistor 34 is opened. The transistor 35 remains closed under the action of a zero signal at the input. H key 3.1-3, H, As a result,

In this mode, the waiting time for the output voltage is 6.1–6, the N key is 3.1–3, the IQ is missing, and its demand is not

exceeds several tens of milli-adoer.

The 3.1 SjN key switches from the Prep mode. to Operation mode at 15 Simultaneous transfer to high-impedance state of input 16.1-16.NC supplying 20 volts to the input voltage path approximately +7 V In this case, 4 due to the fact that the transistor 34 20 4 is open, the base current sharply increases Transistor 35 and it opens Key 3 "1-3, N outputs 6.1-6-6.11 voltage w-1puls of power supply, limited in amplitude to voltage 25 +5 V zener diode 33 and voltage drop at the junction base-emitter transistor 35. Simultaneously in the circuit of the second control input 16.1-16, H

Key 3, an additional 30-volt power pulse appears, approximately 5.6 V,

, From relsim Work key 3.1-3, can be transferred to Preparation mode while simultaneously removing activating effects from input N and input 20 or into Suspension mode when removing activating effects from input 4.1-4, H "In any Transistor 35 abruptly closes these options due to shorting (through the appropriate disconnecting element of block 14) to: bus 10 of zero potential of the parasitic capacitance of the Zener diode 33 along the circuit of the 45th input 11 of the first key element 9

Forcing the process of returning to the initial state of input 16,, K makes it possible, in general, to accelerate the process gQ of returning to the initial state of output b, lt6, H with good power 3.1-Z. power supply. Module 5.1-5, N of the memory stores and stores the code of the number (yes) for the numerical outputs 15 of the T gg device in accordance with the code of the address of the least significant bits of the device (fig. 1, the address inputs of the minor bits of the are shown) Information from mo-.

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A blew of 5.1-5, N is carried out when there is a power supply pulse (+5 V) at its input and an allowed potential at the gate input 4.1-4, N. Module 54l-5., N memory can be performed on fixed memory chips with open collector-type outputs,

The first additional power switch 7 (FIG. 3) works as follows.

In each cycle of accessing the device, the power supply key 7 is sequentially switched to one of two states: Operation, Standby, determined by the state of its control input 11, The output voltage of the supply voltage of the key 7 is connected to the power supply of the key 7. .- Standby mode (initial state), input 1 of key 7 is shorted through the open first key element, 9, and bus 10 of zero potential. The transistor 39 is closed. The switching input 19 is connected to the control input 11 via an open diode 41. In the R. operating mode, the input 1 of the key 7 is disconnected from the zero potential bus 10. Transistor 39 is open. The switching input 19 is connected to the output 8 through the open transistor 39,

The second additional power key 21 (FIG. 3) works in the same way as key 7, but in each cycle of accessing the device switches to opposite states, namely: Standby, Work,. In Standby mode, the switching input 29 of key 21 is connected to its control the input input 23 through the open diode 41; In the Operation mode, the switching input 29 of the switch 21 is connected to the input 8 of the power supply through the open transistor 39.

The first key element 9 (FIG. 4) works as follows. In each cycle of accessing the device, the key element 9 sequentially switches to one of two states: Operation, Standby, determined by the state of its control input 26, In Standby mode (original state) on the control input 26 of the key element 9 is set to zero. The output of element 44 is in a high impedance state. Transistor 45 is open. Mode The operation of the key element 9 is initiated

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In this case, the output of the element 44 goes into a low-impedance state, and the transistor 45 is closed for the duration of the action at its base of a low-level signal.

The second key element 22 (Fig. 4 operates similarly to the key element 21, but in each cycle of accessing the device switches with it to opposite states, namely: Waiting, Operation.

The load elements 12 (resistors) form the standard level of logic 1 signals at the device’s numerical outputs 15. The output of the units 13 and 14 can be made on diodes and connected by cathodes to the input 11 of the first key element 9. The valve elements 17 and 27 can would be made on diodes and anodes connected to step 8. Valve element 28 can be made on diode and by the year connected to the power supply bus 20 of keys 3.1-3.N. Cumulative elements 18 and 29 can be performed on capacitors.

The use of the proposed device allows to reduce the duration of the Preparation mode by 3-4 times.

In addition, the use of the proposed device in semiconductor fixed memory blocks with pulsed power supply allows their performance to be increased by 25-30%. This ensures a low level of the logical O signal at the number of outputs and the minimum required power consumption of the latter when

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Claims (1)

Invention Formula Elekironnoe gadgetry on avt.Sv. W 1334305, characterized in that, in order to improve quickly-: by acting to speed up the process of preparation for work due to additional high-voltage pulses, a second additional power switch was inserted, the power input of which is connected to the terminal for connection power supply source, the second key element, the power input of which is connected to the zero potential bus, and the switching input is connected to the control input of the second additional power key, the element NOT, the input to torogo coupled to the control input of the second element. and a control input, and the output is connected to the control input of the first key element, the second and third valve elements and the second accumulation element, the second valve and second storage elements are connected in series between the output for connecting the power supply source of the second additional switch the third power supply is connected between the common terminal of the first valve and the first storage cell and the common position of the second valve and the second cumulative elements.