JP2778611B2 - Clock loss detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock detecting circuit, and more particularly to a clock disconnection detecting circuit for detecting an abnormal state of a clock for synchronously operating a main unit in a digital communication system.

[0002]

2. Description of the Related Art FIG. 4 is a diagram for explaining connection of a clock detection circuit. The main device is, for example, a device such as a digital exchange, and performs a synchronous operation such as data transfer using a clock CLK input from a reference clock source. The clock disconnection detection circuit is connected between the clock supply line and the main device to monitor the clock CLK as shown in the figure, and the clock CLK sent to the main device is changed to a high (H) level for some reason. Or an abnormal state which does not change and remains at the low (L) level. Such an abnormal state of the clock is referred to as “clock cut”. Naturally, such a clock-cut state makes it impossible for the main unit to perform a predetermined synchronous operation, so that a malfunction occurs therein.
Therefore, it is necessary for the clock loss detection circuit to detect such a clock loss early and generate an alarm ALM in the main device.

FIG. 5 shows an example of a conventional clock disconnection detection circuit. As shown, this circuit has two comparators C
OM1, COM2 and exclusive NOR gate (ENOR)
It consists of. Vref1 and Vref2 are reference voltages supplied to one input of the comparator. The clock CLK corresponds to the input clock of FIG. 4, and the alarm ALM is supplied to the main unit when detecting the clock loss.

As will be described later, the comparators COM1, COM1,
Based on the magnitude relationship between the negative potential V of COM2 and each of the reference voltages Vref1 and Vref2, it is determined whether the clock is normal, abnormal at H level, or abnormal at L level. In the case of the above two abnormalities, the alarm ALM is issued from the ENOR gate. Also, as described later, depending on the type of the gate circuit, the alarm A is set at the H level.
It is possible to distinguish between issuing the LM or issuing the alarm ALM at the L level.

FIG. 6 is an explanatory diagram of alarm issuance / non-issuance of the configuration of FIG. As an initial condition, the potential V is Vref1 and Vre
It is set to the midpoint of f2. Under these conditions,
When the clock CLK is normally input in the form of repeating H / L as shown, the potential at point V is Vref1
Because it is at the midpoint of Vref2 (where Vref1> Vref2),
One input A1 of the ENOR gate is at the H level, the other input A2 is at the L level, the output of the ENOR gate is at the L level, and the alarm ALM is not issued (is not issued).

On the other hand, when the clock CLK is abnormal and fixed at the H level without change, the potential at the point V becomes higher than Vref1 and Vref2, so that both A1 and A2 become L level,
Therefore, the output of the ENOR gate becomes H level, and an alarm ALM is issued. Further, when the clock CLK is abnormal and fixed at the L level without change, the potential at the point V becomes lower than Vref1 and Vref2, so that A1 and A2 both become H level, and the output of the ENOR gate becomes H level. Issues an alarm ALM.

[0007]

By the way, when the clock disconnection detecting circuit shown in FIG. 5 is composed entirely of transistors, there is a problem that the scale becomes considerably large. Also, threshold levels,
That is, if Vref1 and Vref2 are set near the H level or the L level of the clock CLK, it becomes susceptible to external noise and the like, and there is a problem that the comparison operation of the comparator becomes unstable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock loss detecting circuit capable of reducing the size of the circuit as much as possible and reliably detecting a clock loss and issuing an alarm.

[0009]

FIG. 1 is a diagram showing the basic configuration of the present invention. As shown in the figure, the clock loss detection circuit of the present invention includes first to fourth four constant current sources (IS1 to IS1).
4), first to fourth switches (SW1 to SW4) connected thereto, first to third three inverters (INV1 to 3), and first and second capacitors (C
1, C2) and gate circuits (OR, NOR, etc.).

In the illustrated example, the gate circuit is an OR gate, but as will be described later, NOR, AND, NAND,
EOR, ENOR, etc. can be used. Also, V
DD is a supply voltage, which is a first power supply. The second
Is ground (GND). I1 to I4 are currents flowing through the switches SW. In this case I1, I3
Are charging currents to the capacitors C1 and C2, and I2 and I4
Is a discharge current from the capacitors C1 and C2.

[0011]

[Table 1]

Table 1 shows the operating state of each switch SW.
When the input to the switch is at the H level, the switch SW
1, SW3 are turned off, SW2 and SW4 are turned on, and when the input to the switch is at L level, the switches SW1, S
W3 is turned on, and SW2 and SW4 are turned off. That is, the switches SW1, SW3 and the switches SW2,
SW4 is provided with a switch that always performs the reverse operation.

[0013]

[Table 2]

Table 2 is a truth table at each point when an OR gate is used for the gate circuit. As an initial condition,
I1> I2, I3> I4, and when the clock CLK is at the H level, SW1 and SW4 are turned on, and the clock CLK is at the L level.
When the level is at the level, SW2 and SW3 are turned on. As shown in Table 2, when the clock CLK is input, I1
Since> I2, I3> I4, charges accumulate in the capacitors C1 and C2, and the potentials of V1 and V2 become H level.
Therefore, A1 and A2 become L level, and the alarm ALM
Is not issued.

On the other hand, when CLK is fixed at H level, SW
1 is on, SW2 is off, SW3 is off, and SW4 is on. V1 is at H level and V2 is at L level. Therefore, A1 is at L level and A2 is at H level. ALM is issued. Further, when CLK is fixed at L level, S
W1 is off, SW2 is on, SW3 is on, and SW4 is off. V1 is at L level and V2 is at H level. Therefore, A1 becomes H level, A2 becomes L level, and ALM
Is issued.

[0016]

[Table 3]

Table 3 is a truth table when the gate circuit is an AND gate. As an initial condition in this case, I1 <I
2, I3 <I4. According to the same concept as described above, when the clock CLK is normal, A1 and A2 are both at the H level, and the alarm ALM is not issued. On the other hand, when the clock CLK is fixed at H level, A1 is at L level and A1 is at A level.
Since 2 is at H level, an alarm ALM is issued.
Further, when the clock CLK is fixed at the L level, A1
Is H level and A2 is L level.
Issue M.

[0018]

FIG. 2 is a block diagram showing an embodiment of a clock disconnection detecting circuit according to the present invention. In the figure, the present example uses N as a gate circuit.
This is the case where an AND gate is used. TP01, TP0
2, TP05, R1, TN01, TN02, and TN05 are constant current source circuits and correspond to IS1 to IS4 in FIG. TP03, TN03, TP06, and TN06 are switch circuits, and correspond to the switches SW1 to SW4 in FIG.
TP04, TN04, TP07, TN07 are inverter circuits. These transistors are all MO
STP, "TP" is PNP type, "TN"
Indicates an NPN type. As is well known, the former is turned on when its gate is at H level, and the latter is turned on when its gate is at L level.

When the clock CLK is at the H level, the capacitor C1 is charged to the power supply voltage VDD level by the current I1, while the capacitor C2 is discharged to the GND level by the current I4. According to this operation, V1 point and V1 point
The voltages at the two points are compared with the threshold value of the inverter circuit, the H / L levels of the output signals A1 and A2 are determined, and the output and non-emission of the ALM are determined by the NAND gate that receives this. When the clock CLK is at the L level, the output at each point is inverted but operates in the same manner, and a description thereof will be omitted.

FIG. 3 is a diagram showing a configuration in which an output stage for issuing an alarm according to the present invention is a gate circuit. Table 4 shows the magnitude relation between the currents I1 to I4 of the respective constant current sources and truth values showing specific examples of the gate circuit. It is a table. The circuit operation of FIG. 3 is the same as that of FIG. That is, FIG. 1 shows an example in which the gate circuit is an OR gate.

[0021]

[Table 4]

Table 4 is a list of various gate circuits. To issue an alarm ALM at the H level, OR, AND, and EOR gates are used. To issue the alarm ALM at L level, NOR, N
Use AND and ENOR gates. Specifically, it is as follows. Table 4 corresponds to the example of FIG.
2, I3> I4 and the gate circuit is an OR gate. In this case, the alarm ALM is issued at the H level. To issue the alarm ALM at the L level, the gate circuit may be a NOR gate.

Table 4 shows the case where I1 <I2 and I3 <I4. To issue the alarm ALM at the H level, the gate circuit is an AND gate and the alarm ALM is at the L level.
To emit at the level, the gate circuit may be a NAND gate. In Table 4, and, I1> I2, I3 <
In the case of I4 or the case of I1 <I2, I3> I4, the gate circuit is set to an EOR gate to output the alarm ALM at the H level, and the gate circuit is set to output the alarm ALM at the L level. A good choice is an ENOR gate.

[0024]

As described above, according to the present invention,
The comparator and the threshold voltage as in the prior art shown in FIG. 5 can be eliminated, and the input level of the clock is high, so that it is hard to receive external noise, and it is possible to accurately detect the clock break and issue an alarm. Further, the circuit scale can be simplified and downsized.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of a clock disconnection detection circuit of the present invention.

FIG. 3 is a configuration diagram of an embodiment of the present invention in which an output disconnection is a gate circuit.

FIG. 4 is a connection explanatory diagram of a clock detection circuit.

FIG. 5 is an example of a conventional clock loss detection circuit.

FIG. 6 is an explanatory diagram of alarm issuance / non-issuance of the configuration of FIG. 5;

[Explanation of symbols]

 IS1-4 Constant current source SW1-4 Switch INV1-3 Inverter circuit TP01-07 PNP transistor TN01-07 NPN transistor

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 7/00 H04L 25/02 301

Claims (5)

(57) [Claims] 1. A clock loss detection circuit for detecting an abnormality of an input clock, comprising: first and third constant current sources (IS1, IS3) connected in parallel to a first power supply (VDD); First and third switches (SW1 and SW3) connected to the first and third constant current sources, and second and fourth switches connected in parallel to a second power supply (GND). A constant current source (IS2, IS4); a second and fourth switch (SW2, SW4) connected to each of the second and fourth constant current sources; and an input side for receiving the clock (CLK). A first inverter (INV1) having an output connected to the first and second switches, and a second inverter having an input connected to the first and second switches and an output connected to a gate circuit. Inverter (INV2)
A third inverter (INV3) having an input side connected to the third and fourth switches and an output side connected to the gate circuit.
And one terminal is connected to the input side of the second inverter,
A first capacitor (C1) having the other terminal connected to the second power supply, and one terminal connected to an input side of the third inverter;
A second capacitor (C2) having the other terminal connected to the second power supply; and the gate circuit for receiving an output of the second inverter and an output of the third inverter and issuing an alarm (ALM). The first to fourth constant current sources (IS) are switched by the first to fourth switches (SW) to charge the first and second capacitors, and the first to third constant current sources (IS) are charged. A clock disconnection detection circuit through the inverter and the gate circuit. 2. By changing the magnitude relationship between the charging current to the capacitor and the discharging current from the capacitor,
2. The clock loss detection circuit according to claim 1, wherein the alarm issuance and non-emission times are varied regardless of the clock frequency. 3. The clock according to claim 1, wherein the alarm issuance and non-emission time are varied irrespective of the frequency of the clock by changing the capacitance value of the first and second capacitors. Disconnection detection circuit. 4. The alarm output and non-output time irrespective of a frequency of the clock by changing a threshold voltage of the first to third inverters. Clock disconnection detection circuit. 5. The clock disconnection circuit according to claim 1, wherein a logic gate of said gate circuit is changed according to a magnitude relation between a charging current to said first and second capacitors and a discharging current from said capacitor. Detection circuit.