SU1363170A1 - Generator of n-power reciprocal sequences - Google Patents

Abstract

The invention relates to computing and is intended to generate weight sequences of return sequences of various orders. The purpose of the invention is to expand the functionality for the very generation of weights of various return sequences. The generator contains n resistors 1, block 2 synchronization, adder 3, block 4 of switching and input of initial conditions, n elements AND, n elements OR. The goal is achieved by introducing a block of 4 switches and entering the initial conditions for the n elements AND, n of the OR elements. 1 hp f-ly, 2 ill.

Description

113631

This invention relates to a computational technique and can be used to simulate a series of different recurring sequences. g

Expression (1) allows one to model a unary number system and a huge class of return sequences.

Sy (n)

0 when

1 at Oinsj;

J VA

(one)

L

S- () at.

As,, l, expression (l) defines the classical binary number system.

The purpose of the invention is to expand the functionality due to the ability to generate sequences of weights of different-shkh return sequences.

The essence of the invention consists in the implementation of the expression (1).

FIG. 1 shows a n-th order return sequence generator; in fig. 2 - switching unit and input of initial conditions.

The generator contains n bit registers 1.1; 1,2 ... 1, p (where). block 2 synchronization, adder 3, block 4 commutation and input of initial conditions, n elements AND 5.1, 5..2 ... 5.P, n elements OR 6.1.6.2 ... 6.P5 information outputs 7.1.7.2 , 7.p.

The switching and input unit 4 includes the first decoder 8, the generator unit code 9, the first element OR 10, the n-bit register 11, the comparison circuit 12, the parallel adder 13, the second decoder 14, the generator 15 of the return code of the unit, the second, the OR 16 element, two delay elements 17 and 18, the AND element 19, the third element 20, the control input 21, the reset input 22, the group of AND 23 elements. K..23.n, n the triggers 24.1 ... 24.P the first group n outputs 25.1 ... 25.P5 the second group n outputs 26.1 ... 26.P5 the first group n inputs 27.1 ... 27.P, the second group n inputs 28.1 ... .28.P, output 29.

 Unit 4 of switching and input of initial conditions serves for input of initial conditions in i of the first registers, as well as connection to the output of the respective registers 1-p., Depending on the A, B, y accepted for this case.

g

0

If

20

25

zb 40

45

50

55

702

In order to consider the operation of the generator of recurrent sequences of the nth order, we first analyze the operation of the switching unit and the input of initial conditions.

Block switching and input of the initial conditions as follows.

The input values 27.1, 27.2 ... 27.p receive the value (| f + B) in the binary classical number system, write to register 11 and enter the inputs of the decoder B. B. Depending on the value (j + B) at the output of the decoder 8 Logical 1 appears with the number (y + B), which through the element OR 10 turns on the generator, 9 and opens the corresponding element g AND .23.1, 23.2 ... 23.p. The generator 9 generates a serial code unit, which, through the element And enters the corresponding output bus 25.1, 25.2 ... .25 .. p. In the meantime, the input buses 28.1, 28.2 ... 28.p arrive at values (2; j + A) in the binary classical number system and are written to the triggers of the parallel adder 13. By the signal on the control bus 21, the value (2J + A) is output from the adder 13 to the inputs of the comparison circuit 12 and the decoder 14. The signal from the output of the delay element 17 compares the values (2X + A) and (+ B) in the comparison circuit 12, a signal (25 + A) is output (y + c) ipi () (y + b). If () e: (x + B), the THEN signal through the MJM 10 element is fed to the control input of the NIN decoder 14, the output of the decoder: torus with the number () appears signal 1, which is stored by the corresponding trigger 24.1 output cable 26.1. The same signal starts the generator 5, which outputs a parallel code to the inputs of the su; Mator 13, the return code of unity 1. By the same signal, delayed in the delay element 18, the result is received at the input of the comparison circuit 12, which compares the values (2ХЧ-А-1) and (у + В). If {2J4-A-1) (J + B), then the process just described is repeated until (2V + A-i) becomes less than y + B. In this case, the signal is fed to the input of the element 19. If generator 9 has already issued code 1, then the generator 2 synchronization unit is turned on from the output of element AND19 via bus 29-a.

The generator 15 generates an inverse code of a unit of equal to the size parallel to the adder 13.

Thus, unit 4 of commutation and input of initial conditions enters into the first (J + B) registers the value of one and connects the outputs of registers l.i with numbers, -J + A to the input of adder 3 of the generator of return sequences of the n-th order

If it is necessary to simulate another return sequence, a signal is sent to the reset bus 22, then new values (Y + B) and (2y + A) are entered.

After the initial conditions are entered and the connections of the corresponding li registers with the number -jf + AJ are formed, a control signal is fed to the inputs of the summer 3 to the input of the synchronization unit 2, which generates a clock signal to the li registers and the summer 3. The rewrite of information from the youngest to the old is done, and the register 1.1 records the number written by the result of the summation of the contents of the registers li with numbers i x + B; 2 (5 + + A. Next, the synchronization block again outputs a clock signal to the registers, a bit later - to the adder, a similar process of rewriting numbers into the following registers l.i and summation occurs. The information is removed from the information output 7 (+ V).

Obviously, by changing the values of A, B, X in expression (1), any return sequence can be synthesized, which is used as a basic function of the number system with natural redundancy.

Claims (2)

Invention Formula one . A n-th order recurrent sequence generator containing n registers, a synchronization unit, an adder, the first output of the synchronization unit is connected to the control inputs of all registers, the second output of the synchronization unit is connected to the control input of the adder, the output of the first register is connected to the first information output of the generator, that is, in order to extend the functionality by generating a sequence of weights of various returnsQ g n 5 d five 0 5 n sequences, AND elements, the switching unit and the input of the initial conditions are entered into it, the outputs ix (, ..., n) of the registers are connected to the first inputs of the corresponding ix AND elements, the second inputs of which are connected to the corresponding the outputs of the first group of p outputs of the switching unit and input of initial conditions, each i-th output of the second information group of outputs of which is connected to the (n-i + l) -My input of all OR elements from the first to the i-th group of OR elements, the adder output connected to (n + 1) th in the course of the first element OR groups, ix register outputs are connected to (n – i + l) -My input (i + l) -ro of the element OR group, outputs of ix elements AND are connected to the corresponding inputs of the adder, the trigger input of the synchronization unit is connected to the trigger output of the switching unit and input initial conditions, the outputs of the registers from the second to the nth are connected to the corresponding outputs from the second to the nth generator. 2. The generator according to claim 1, characterized in that the switching unit and the input of initial conditions contain two degchifratora, parallel adder, unit code generator, generator return code generator, two delay elements, three elements OR, comparison circuit, n-bit register , element I, a group of n elements AND, n triggers, where the input of the n-bit register and the input of the first decipher is connected to the first group of information inputs of the block, the outputs of the descrambler are connected to the first inputs of the AND elements of the group, to the n inputs of the first element OR, the output koto connected to the start input of the generator of the unit code, the first output of which is connected to the second inputs of elements AND of the group, the second group of information inputs of the block is connected to the first group of information inputs of the parallel adder, the output of which is connected to the group of information inputs of the second decoder and the first group of inputs of the comparison circuit, the second group of inputs of which is connected to the output of the n-bit register, the control input of the block is connected to the first input of the second OR element, whose output is connected to the control input The parallel adder and through the first delay element to the control input of the comparison circuit, the outputs of the second depigraphrr are connected to the installation inputs of the triggers, the outputs of which are connected to the first group of information outputs of the unit, the reset input of which is connected to the reset inputs of the triggers, the output of the reverse coder ya units are connected to the second group of inputs of a parallel adder, the input of the lower bit of which is connected to the transfer output of the higher bit of the n-bit register, the outputs of the elements of the And group are connected to the second group of informational outputs of the block, vyFig. 2 VNIIPI Order 6362/39 Circulation 671 Subscription Proizv.-polygr. pr-tie, Uzhgorod, st. Design, And the starting stroke of which is connected to the output of the element And, the first input of which is connected to the second output of the generator of the unit code, the second input of the element AND is connected to the output. Change the comparison circuit, the outputs More and Equal to which are connected to the first and second inputs of the third element OR whose output is connected to the control input of the second decoder, the start input of the generator of the return code of the unit and through the second delay element to the second input of the second element OR,