SU1352666A2 - Apparatus for synchronous detection of phase-manipulated signals - Google Patents

Abstract

The invention can be used to receive discrete information transmitted over a communication channel using pseudo-random phase telegraphy signals. Compared with the main invention of the author. St. No. 1312754 in the proposed increase in detection accuracy when extending the limits of carrier frequency variation. The device contains a filter 1, a phase detector 2, a decisive block 3, a delay block 4, an adder 5, a voltage driver 6, an additional delay block 7, an additional adder 8, a subtractor 9, a trailing pseudo-random sequence generator (PSP) 10, phase manipulator 11, additional subtraction unit 12 and phase discriminator 13. Tension shaper 6 consists of bottom limiters 14, 17, 22, 25, comparison blocks 15, 19, keys 16, 20, and limiters 18, 21, 23, 24 voltages from above. The following generator PSP 10 consists of a phase detector 26, a former 27 and a clock synchronization unit PSP 28. Blocks 10–13 are introduced. Using the blocks 10, 11, the information sequence of the pseudo-random video signals is extracted from the radio signal, transformed into a sequence of binary impulse pseudo-random code combinations, combining the latter in time with the generated reference memory bandwidth generated by the subtraction unit 9, and converting the wideband bandwidth input signal into narrowband simple signal. 1 hp f-ly, 1 ill. p (O oh el GhE o: O5 O5 14)

Description

The invention relates to synchronous communication systems and can be used in equipment designed to receive discrete information transmitted over communication channels using pseudo-random signals of phase telegraphy, the carrier frequency of which is subject to change.

The purpose of the invention is to improve the detection accuracy while expanding the range of variation of the carrier frequency.

The drawing shows a structural electrical circuit of the proposed device.

The device contains a filter 1, a phase detector 2, a decisive block 3, a delay block 4, an adder 5, a voltage driver 6, an additional delay block 7, an additional adder 8, a subtraction block 9, a trailing generator of a pseudo-random sequence 10, a phase manipulator

1I, additional subtraction unit

12, phase discriminator 13, the voltage driver 6 being composed of a voltage limiter 14 at the bottom, a comparison unit 15, a key 16, a voltage limiter 17 at the bottom, a voltage limiter 18 at the top, a comparison unit 19, a key 20, a voltage limiter 21 from above, limiter 22 voltages from below, limiter 23 voltages from above, limiter 24 voltages from above, limiter 25 voltages from below

The following pseudo-improved sequence generator 10 consists of a phase detector 26, a driver 27 and a clock synchronization unit of a pseudo-random sequence 28

The device works as follows.

A binary combination of code pulses, corresponding to a pseudo-random sequence of intrapulse modulation of a pseudo-random signal distorted by noise, is supplied to one input of a phase manipulator 11 by following a pseudo-random sequence generator 10.

With the help of phase manipulator 11, the signal is manipulated, as a result of which the signal is convolved (converted) into a narrowband simple signal, further

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processing of which is performed by filter 1.

Using filter 1, the signal is cleared of interference and then fed to the input of the phase detector 2, to the input of the adder 5 and the input of the adder 8.

At the output of the phase detector 2, detected signals appear, which are fed to the input of the decision block 3, which decides which symbol was transmitted,

As a reference voltage supplied to the second input of the phase

5 of detector 2, the voltage allocated at the output of the block is 1 and 9;

So that the current value of the reference oscillation corresponds to the current value of the time-varying frequency of the carrier oscillation, the delay time of the delay unit 4 and the additional delay unit 7 is automatically adjusted, the essence of which is as follows. The reference voltage allocated at the output of the subtraction unit 9 is fed to the second input of the phase discriminator 13, to the first input of which is fed

0 is formed by using an additional subtraction unit 12, the difference of the voltages allocated to the second outputs of the delay unit 4 and the additional delay unit 7.

g The electronic adjustment of the time of the delay units 4 and 7, which are included in the system with a closed control cycle, is set so that, for any value of the control, on the Q, the voltage remains unchanged and

less than one, the ratio of the signal transit time from the input to the first output to the signal transit time from the input to the second output. Wherein

By selecting the parameters of the delay blocks 4 and 7, the signal transmission time interval to the first output is automatically set to one or several periods of the input signal carrier frequency, and the signal transmission time interval to the second output is set to the same number of half-periods of the signal carrier frequency.

It is advisable to choose the parameters of the delay elements so that at the center frequency of the oscillating carrier the phase difference between the oscillations arriving at the inputs of the phase disk.

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The iminator i3 was 0, glad. In this case, the deviation of the carrier frequency from the center frequency of the sound is generated by changing the phase angle between the input oscillations of the phase discriminator 13 and setting the control voltage 13 of the corresponding sign and level at the output of the phase discriminator 13.

By introducing into the device of the phase detector 26 and the former 27, the radio-signaling of the information sequence of opposite pseudo-random signals in the form of a binary sequence supplied to the first input of the clock synchronization unit of the pseudo-random sequences 28 is achieved.

Until the time sequence combines the convolution of an input pseudo-random signal characterized by a wide band spectrum, a simple signal characterized by a narrow band of the spectrum does not occur and filter 1, whose transparency band is matched with the spectrum band of a simple signal, passes to the inputs of the adders 5 and 8 and phase detector 2, only those components of the spectrum of the signal generated at the output of the phase manipulator 11, which fall into the transparency band of the filter I the response of the signal components that have passed through The output of the filter 1, at the output of the subtraction unit 9, is the reference voltage supplied to the second inputs of the clock synchronization unit of the pseudo-random sequence 28 and the phase detectors 2 and 26. The information sequence of the pseudo-random radio signals arriving at the second input of the phase manipulator 1I is simultaneously sent to the first input signal the input of the phase detector 26 converts the information sequence of pseudo-random radio signals into the information sequence of pseudo-random video signals, From to stroke phase detector 26 information sequence of pseudorandom generator 27 through the video signal, converts the sequence of pseudo-random video signals in sequence. pseudorandom code combinations of binary pulses, is applied to the first input of a pseudo-random clock synchronization unit sequentially

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28, since a signal voltage with a high signal-to-noise ratio cannot be generated from a filter 1 output signal, the binary combination of binary pulses at the output of the driver 27 will not coincide in all positions with the pseudo-random sequence of the intrapulse modulation of the signal.

a clock synchronization unit 28 performs pseudo-random sequence is repeated delay variation generated pseudo-random sequence, leading to the reconciliation of its temporal boundaries with time boundaries of a pseudo-random sequence generated on the output of shaper 27. When combining the pseudorandom sequence are correlated, the input wideband pseudo-random signal at the output of the phase manipulator 11 is rolled into a narrowband simple signal, the signal-to-noise ratio in the formation circuit is ornogo voltage sharply increases and increases the degree of correspondence formed at the output of shaper 27 pseudowords tea sequence pseudorandom reference sequence. The response at the output of the correlator included in the clock synchronization block of the pseudo-random sequence 28, reaching a threshold value, causes the clock synchronization block of the pseudo-random sequence to switch to synchronous tracking of the signal parameters.

The carrier oscillation or reference voltage is formed as follows.

The noise-mapped phase-manipulated signal passing through filter I affects the input of the adder 5 and the input of cvMMaTopa 8,

To the other input of the adder, 5, the voltage of the response of the delay unit 4 is applied to the impact coming to the input of the delay unit 4 from the output of the adder 5, the response voltage of the delayed unit 4 is delayed by time

1 n / f, p 1,2,3 .. ,, N, s, where f. - -carrier input frequency

phase-shifted signal, input voltage adder 5.

The carrier frequency of the input phase-shift keyed signal can be considered5

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as a function of time, i.e. f f (t), and the delay time of the delay unit 4 as a variable value dependent on the variable frequency of the carrier wave:

i, f, (t). .

Similarly, the second input of the additional adder 8 is supplied with the voltage of the response of the additional delay unit 7 to the input to the input of the additional delay unit 7 from the output of the additional adder 8, the response voltage of the additional delay unit 7 is delayed by time 2 1 (t) output additional adder voltage is -8.

The voltage generated at the output of the delay block 4 through the voltage limiter 14 from below, which limits the incoming voltage to its input at the bullet level, acts on the first input of the comparison unit 15, and from the voltage limiter 8 from above, which the restriction of the voltage arriving at its input from above on the zero level affects the first input of the comparison block 1 9,

The voltage generated at the cy output in atopa 5, through the voltage limiter 22 from below, which limits the incoming voltage to its input at the zero level, affects the second input of the unit 15s through the voltage limiter 23 from above, which performs the limitation The incoming voltage at the top of the input at the zero level acts on the second input of the reference block 19.

The voltage generated at the output of the comparison unit 15, which is the result of subtracting the voltage acting on its first input, from the voltage acting on its second input, goes to the first and second inputs, respectively, keys 16 and 20, and the voltage generated at the output of the comparison unit 19, which is the result of subtracting the voltage acting on its first input, from the voltage acting on its second input, goes to the first and second inputs, respectively. Keystroke keys 20 and 16.

Key 16 (20) depending on the voltage level acting

to its second input, either sends a voltage to the output acting on the first input, or delays it. If the key 16 (20) is in the closed state, then on its output it takes a zero value.

The voltage generated at the output of the key 16, through the voltage limiter 17 from below, limiting the flow (its input voltage from the bottom at the zero level,. Is fed to the input of the adder 5, and through the voltage limiter 24 the restriction of the voltage arriving at its input from above at the zero level is applied to the third input of the additional adder 8,

Q The voltage generated at the output of the key 20 through the voltage limiter 21 on the top, limiting the incoming to its input -. rules above the zero level

; j is fed to the input of the adder 5, and through the voltage limiter 25 from below, which limits the voltage arriving at its input to the bottom at the zero level, is applied to the fourth.

The 0 input is an additional adder 8. A reference voltage is generated at the output of the subtractor 9.

If the polarity of the voltage at the output of the adder 5 coincides with the polarity of the voltage at the output of the delay block 4, then in accordance with the sign of the polarity eg: senp at the outputs of the adder 5 and block 4 of the delay 4 one of the keys 16 and 20 is in an open state nii. If the indicated voltages have different polarities, then both keys 16 and 20 are in the closed state.

In the open state, the key 16 passes the inputs to the inputs of the limiters 17 and 24, the voltage generated at the output of the comparison unit 15. Similarly, in the open state, the key 20 passes the inputs of the limiters 21 and 25

0 is the voltage generated at the output of the comparison block 19.

At the input interval of the filter 1 of the first segment of one-sign elements of a pseudo-random intraimg pulse modulation, the response amplitude of the harmonic oscillation input segment at the output of adder 5 exceeds the amplitude of the input-segment response of the harmonic oscillation

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the output of the delay unit 4, and in the transmission interval of the first pseudo-random modulation segment the polarity of the voltage at the output of the adder 5 coincides with the polarity of the voltage at the output of the delay unit 4, while, in accordance with the operation of the device, the oscillations from the output of the adder 5 to the inputs are provided cy Imathor 5, connected to the outputs of elements 21 and 17 along the positive feedback circuits, and passing oscillations from the output of the adder 5 to its inputs, connected to the outputs of limiters 21 and 17 along the negative and positive circuits Your feedback.

In the interval of arrival at the input of the filter 1 of the radio pulse of the first segment of the one-sign elements of intra-pulse pseudo-random modulation, limiters 24 and 25 do not allow oscillations to the inputs of limiters 24 and 25 from the outputs of keys 16 and 20 to the third and fourth inputs of the additional adder 8. at the output of the additional adder 8, covered by a positive feedback circuit containing an additional delay block 7, an oscillation is selected, whose frequency and phase corresponds to the frequency and phase of the radio pulse, after the amplitude of the signal at the output of the adder 5, the oscillation generated at the output of subtractor 9, represents the result of the subtraction of the oscillation generated at the output of the additional adder 8, from the oscillation formed at the output of the adder 5. At the same time, the frequency and phase of the oscillation generated at the output of the subtraction unit 9 correspond to the frequency and phase of the carrier phase-manipulated signal used as a reference voltage wives

When receiving the next segment of one-sign elements of a pseudo-random intrapulse modulation that does not coincide in sign with the first segment, the response amplitude of the input radio frequency pulse of the pseudo-random modulation segment at the output of the adder 5 is less than the response amplitude of the input radio pulse of the pseudo-radius segment 56

modulation at the output of the delay block 4, the polarity of the voltage at the output of the adder 5 coincides with the polarity of the voltage at the output of the delay block 4. At the same time, the oscillation from the output of the adder 5 to the third and fourth inputs of the additional adder 8, and no oscillation from the output of adder 5 to the

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its inputs through the limiters 17 and 21. At the same time, the amplitude of the oscillations at the output of the adder 5 is mediated by the decay. t, and the slope of the oscillations at the output of the additional sumator B rapidly decreases to zero and then also increases exponentially, reaching a certain value.

The oscillation phase at the output of the adder 7 after the amplitude passes through zero abruptly changes by T radians. The oscillation generated at the output of the subtraction unit 9, representing the result of subtracting the oscillation generated at the output of the additional adder 8 from the oscillation generated at the output of the adder 5, does not change the phase set at the moment of arrival of the first segment of the single-sign pseudo-random intrapulse modulation elements.

If the polarity of the input response voltage at the output of the adder 5 is opposite to the polarity of the input response voltage at the output of the delay unit 4, which is possible if there is a change in the carrier frequency or interference in the communication channel, then the inputs of the adders 5 and 8 connected to output voltage generator 6, the oscillation from the output of adder 5 does not pass, In this case, the amplitudes of the oscillations at the outputs of homotope 5 and 8 slowly decrease exponentially, and at the output of the subtraction unit the oscillation retains the oscillation phase nor, established at the moment when the first segment of the one-sign elements of the pseudo-random intrapulse modulation arrives at the device input.

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ABOUT

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Claims (2)

Formula Eteni one . Device for synchronous phase shift detection 9 signals auth. St. № 131275А, different topics what. In order to increase the accuracy of detecting the expansion of the carrier frequency variation limits, a sequentially connected pseudorandom sequence generator and a phase manipulator, as well as an additional subtractor and a phase discriminator connected in series, are introduced, the first input of the next pseudo random sequence generator is combined with the second input of the phase manipulator, and is the input of the device for the synchronous detection of phase-mapped signals, the output the manipulator is connected to the input of the filter, the output of the subtraction unit is connected to the second inputs of the next generator of the pseudo-random sequence and phase discriminator, the output of which is connected to the second 5266610 the two inputs of the delay unit and the additional delay unit, the second outputs of which are connected to the corresponding inputs of the additional subtraction unit. 2. The device according to claim 1, wherein the tracking generator of a pseudo-random sequence consists of a series-connected phase detector, a former and a clock synchronization unit of a pseudo-random sequence, the first input of the phase detector being the first input of a tracking pseudo-random generator sequences, the second input of which is the combined second inputs of the phase detector and the clock synchronization block of the pseudo-random sequences, the output of which is servo output pseudo-random sequence generator, 15 20