SU1341649A1 - Device for determining number of subgraph nodes of graph - Google Patents

Abstract

The invention relates to computing and can be used to solve combinatorial problems, such as isolating related subsets, while reducing hardware costs. The device contains a group of elements OR 1.. .1 ,, group of triggers 2. ..2, two groups of elements AND 3 ... 3, 17 ... 17, block 4 tasks of topology, differentiating elements 5 ... 5, elements OR 6 and 10, shift register 7 , two groups of registers 8 ... 8, 18, ... 18, trigger 9, input 11 set to zero, generator 13 clocks, two elements And 12 and 14, distributor 15 pulses, element 16 delay, nodes 19. ..19 indications of the number of vertices, nodes 20 ... 20 indications of the numbers of the vertices, counter 21, where n is the number of vertices of the graph under study, and k is the number of subgraphs of the graph under study. 2 Il. Ш 1 (Л СА: д; ет со

Description

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The invention relates to computing and can be used in the construction of specialized devices for the automated design of electronic and computer equipment, as well as in solving problems of communication network optimization.

The purpose of the invention is to reduce hardware costs by reducing the group of meters.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - implementation of the task block of the graph topology.

The device contains a group of elements OR, a group of flip-flops 2, the first group 3 | -3 elements AND, a block 4 specifying the graph topology, differentiating elements, the first element OR 6, the shift register 7, the first group of registers (s, trigger 9, the second element OR 10 , the input 11 of the installation in the device, the first element And 12, the generator 13 clock pulses, the second element And 14, the distributor 15 pulses, the element 16 delay, the second group of elements And, the second group of registers, display nodes 19, -19 numbers of vertices, nodes indication of vertex numbers, counter 21.

The block for setting the topology of a graph contains n identical models of vertices, each of which contains elements AND 22 and 23, elements OR 24, elements AND 25-27, the j-th input 28 of the block specifying the topology, inputs 29-32 of the j-th group of the block topology assignments, output 33 topology assignment blocks and the OR element 34,

The device works as follows.

Before starting work on bus 11 for triggers 2, -2 and 9, shift register 7, registers 8, | -8 |, the distributor 15 pulses, which is also a shift register.

counter 21 and registers 18i-18 feeds 1 p

c. the initial state setup signal. At the same time, at the zero outputs of all bits of the register 7, unit potentials are established, which cause the appearance of a single signal at the output of element 14. This signal records the unit at the first digit of the distributor 15 and through element 16

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five

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five

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five

delays and the I.PI 1 element at the trailing edge triggers trigger 2 into a single state. A single potential from the output of this trigger enters the input of the first vertex of block 4, the graph topology, and appears at the output of the first vertex and at the outputs of all those vertices that form the set of connected vertices. Through the differentiating elements 5 -5, single impulses from the excited outputs (graph vertices) of block 4 arrive through the elements OR 1j-1 to the single inputs of the corresponding triggers, which go to the single state, fix the associated subgraph, Single pulses from the differentiating elements 5: - 5 are written to the corresponding bits of the shift register 7, as well as register 8, since at the moment the resolving potential is on the first output of the distributor 15 and, moreover, any of these pulses through the element OR 10 is reused Diet trigger 9 in one state. When this opens, the element And 12 and the clock pulses from the generator 13 begin to flow to the shift input of the register 7,

Each clock pulse shifts the register code 7 by one bit. In this case, every unit since the last bit of register 7 is read into counter 21. The reading occurs until register 7 is completely reset. For example, if code 1001100 is recorded in register 7, then the first two clock pulses to write to counter 21 do not give, the third and fourth pulses record two units, then the fifth and sixth pulses of the state of counter 21 also do not change and the seventh pulse records the third unit in counter 21. This indicates that the first subgraph consists of three connected vertices, whose numbers 1, 4 and 5 are written in register 8 ,. When resetting the register 7 on its

zero outputs appear single potentials that open up the element. You are And 14, 17, through which the contents of counter 21 are read into a register. One clock pulse of the oscillator 13 passes through the element I 14, writes a unit to the second digit of the distributor 15 pulses and thereby allows writing to register 18 and register 8. This clock name3

the pulse through delay element 16 resets to counter 21, and after passing through element 6 or 6, flips trigger 9 to the zero state, thereby blocking the clock pulses to register 7, and through one of the open elements 3, -3, sets in the one state, that of the flip-flops 2, -2, preceded by the flip-flops, set in the single state, is more equal.

In accordance with the above example, trigger 2 is translated into a single state, which allows you to select a new vertex of the graph that was not included in the first subgraph, and similarly to the described one, excite all vertices that form the second connected subgraph. At the same time, the numbers of the vertices of the second subgraph are also recorded, but already in register 8, the corresponding triggers are set to one, the code is written to register 7, and trigger 9 is set to one in Element 10. After this, the matching from register 7 begins in the counter 21 the number of vertices of the second subgraph. After zeroing the register 7, the clock pulse moves the unit to the third output of the distributor 15 pulses, and through the delay element 16 it goes to that of the flip-flops 2, -2 that have the minimum index untranslated. If all the triggers are in a single state, this clock pulse appears at the output of the AND 3 " element, the signal from which stops the operation of the device, blocking by means of the OR 6 element, the trigger 9 and the AND 12 element the passage of the clock pulses to the register 7 , and gives the resolution signal at angles 19;, - 19 | and 20 20 indications. In this case, the number of vertices in each subgraph and their numbers are highlighted accordingly.

The unit for setting the topology of graph 4 makes it possible to transmit a signal to the output of all connected vertices, if it exists at the input of at least one of them. The block allows you to display the topology of any graph on n specified vertices. For this, each veryin of the graph is mapped by an OR 34 element with n-1 number of inputs, And 22 and 23 elements, and ele166A94

coping OR 24, and for displaying edges that can connect any vertex with all the others, use n-1 element AND 25-27,

If a given vertex participates in a graph, then a single potential must be applied to input 29, if certain edges participate in the graph, then

Q to the corresponding inputs 30, 31 or 32, you must also apply unit potentials. In this case, the element And 22 prohibits the passage of signals along the edges from the vertex participating in the graph

15 to non-participating, and And 23 performs the prohibition of iteration of non-participating vertices in the graph. When fed to the input 28 of one of the vertices of the unit potential, it appears at the outputs

2Q 33 all vertices. In accordance with the described operation of the device, in register 18, 4 vertices are fixed, which are displayed on node 19, indications, and in register 8, are fixed

25 numbers of vertices that are displayed on node 20 of the display.

The block structure of the graph topology allows you to display any topology of both oriented and

30 undirected graphs, each edge of which is mapped by a pair of oppositely directed edges connecting two vertices.

Claims (1)

Invention Formula A device for determining the number of vertices of subgraphs of a graph, comprising a clock pulse generator, a group of n elements OR, where n is the number of vertices of the graph under study, the first group of n elements AND, a group of n triggers, n differentiating elements, the set topology block, the second group of k elements I, where k is the number of subgraphs of the graph under study, pulse distributor , shift register, the first group of k registers, the delay element, k nodes indicating the number of vertices, k nodes indicating the numbers of the vertices, two OR elements, two AND elements, trigger, the output of the clock generator connected to the first inputs of the first and second elements And, the output of the first element And connected to the clock input of the shift register, the information output of which is connected to the second input of the second element And whose output is connected 5, 13 to the first input of the pulse distributor mode setting and to the input of the delay element whose output is connected to the first input of the first OR element, to the first input of the first OR element of the group, to the first inputs of the AND elements of the first group, to the installation inputs in the O registers of the first group, register shift, group triggers, to the second input of the setting of the pulse distributor mode, to the second input of the first OR element, and to the installation input in the device O, the i-th output of the pulse distributor, where i 1, ..., k, is connected to the first input i -ro element and second group and to the input of the read-write i-ro register of the first group, the outputs of the first and second elements OR are connected respectively to the installation input in O and to the installation input in 1 trigger, the output of which is connected to the second input of the first element AND, output j-ro the element of the OR group (j 1,. .., p) is connected to the installation input in 1 j-ro of the group trigger, the output j-ro of the group trigger is connected to the (j + 1) -My inputs of the AND elements from j-ro to n first group and to the j-th input of the topology assignment block, output of the 1st element AND of the first group, where 1 1, ..., n - 1 |, is connected to the first input (1 + 1) of the first element and I-UDi group output of the nth element of the first group and connected to the third input of the first OR gate and to the control inputs 96 nodes indicating the number of vertices and vertex numbers, jH, the group of inputs of the device graph topology setting is connected to the jth group of inputs of the topology specification block, the jth output of which is connected to the input j-ro of the differentiating element, the output of which is connected to information inputs of jx bits of registers the first group is the information input of the j-ro bit of the shift register, the j-th input of the second element I.Sh. and the second input of the OR element of the group, output j-ro the register of the first group is connected to the information input of the i-ro node indicating the numbers of the vertices, which are feeling in order to reduce hardware costs, in the device entered the counter and the second group of k registers 5 and the shift register transfer output is connected to the counter input of the counter, the i-th information output of which is connected to the second input of the element And the second group, the output of the second element And connected to the third inputs elements of the second group, the installation input in the device O is connected to the inputs of the installation in the Oh counter and the registers of the second group, the output of the i-ro element AND the second group is connected to the information input of the i-ro register of the second group, the output of which Go is connected to the information, input i-ro; node display the number of vertices. Compiled by V.Smirnov Editor M.Dylyn Tehred M.Didyk Proofreader A.Obruchar Order 4438/53 Edition 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Design, Fi.2