SU1339829A1 - Master generator of multiphase quasisine voltage - Google Patents

Abstract

The invention relates to a converter technique and can be used in modulation type frequency converter control systems. In order to expand the functionality, a second counter 2 was introduced with a division factor equal to the number of phases of the output voltage, a decoder 11, an adder 8, a multiplexer 7, a demultiplexer 10, code sensors 4, 5, 6 and memory registers 12, 13, 14 by the number of phases of the output voltage. Using these elements, the registers in memory 12, 13, 14 are periodically fixed, followed by digital-to-threshold conversion of discrete sampling codes of sinusoidal voltage of different phases of the output voltage in accordance with the current state of the counter 3 and taking into account the phase shift codes generated by setting codes 4 , 5, 6. The master oscillator of a multi-phase quasi-sinusoidal voltage allows changing the phase shift of the output voltages and, moreover, is used to form a multi-phase system In a single voltage, there is one permanent sling device. 2 Il. (L DO: about 1 f (/ gg

Description

The invention relates to a conversion technique and can be used in modulating-type frequency converter control systems.

The aim of the invention is to expand the functionality of the device.

FIG. 1 shows a generalized functional diagram of the device; in fig. 2 - signal plots explaining the operation of a device that forms a three-phase system of output voltages.

The device contains 1 clock pulse generator, counters 2 and 3, setpoint adjusters 4-6, multiplexer 17, adder 8, read-only memory 9, demultiplexer 10 decoder 11, memory registers 12-14 and digital-to-analog converters 15 - 17. Generator output clock pulses are connected to the input of counter 2 with a division factor equal to the number of phases of the output voltage, the outputs of which are connected to the control inputs of multiplexer 7, demultiplexer 10 and the inputs of the decoder 11, one of the outputs of counter 2 is connected to the input of counter 3. You the counter 3 moves are connected to the first inputs of the adder 8, the second inputs of which are connected to the output of the multiplexer 7, whose information inputs are connected to the outputs of the 4-6 setpoint controllers. The outputs of the adder 8 are connected to the inputs of the permanent storage device 9, the outputs of which are connected to the information inputs of the demultiplexer 10. The outputs of the demultiplexer 10 through memory registers 12-14 are connected to the inputs of digital-to-analog converters 15 17 whose outputs are the outputs of the device. The inputs of the same control registers 12-14 memory connected to the corresponding outputs of the decoder 1 1.

The device works as follows.

Under the action of the clock pulses from the output of the clock pulse generator 1 (Fig. 2, Uj), the counter 2 divides the frequency of these pulses into. m times (where m is the number of phases of the output voltage of the device), thus forming a binary code (Fig. 2, i) at the output, synchronously controlling the operation of multiplexer 7, de0

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multiplexer 10 and decoder 11. Frequencies divided by frequency m times the clock pulses from one of the outputs of counter 2 are fed to the input of counter 3. Suppose that at the initial moment of time counter 2 is reset. In accordance with the code on the control inputs of the multiplexer 7, the demultiplexer 10 and the inputs of the decoder 11, the following switchings are made: the decoder 11 opens the memory register 12, the multiplexer 7 connects the outputs of the setpoint 4 of the code to the second

g to the inputs of the adder 8, the demultiplexer 10 connects the outputs of the persistent storage device 9 to the inputs of the register 12 of the memory. In this case, the output of the adder 8 generates the binary code of the address (Fig. 2, Ug) for the persistent storage device 9, obtained by summing the code at the output of the counter 3 (Fig.) And the code at the output of the setpoint 4 of the code. The code on the output of the setpoint 4 of the code determines the phase shift of the first output voltage U, (usually it is assumed to be zero). Accordingly, a discrete sampling code of a sinusoidal voltage of the first phase is generated at the output of the permanent storage device 9 (Fig. 2, U ), determined by the current state of the counter 3 at zero time, which is fed to the input of memory register 12. With the arrival of the clock pulse, the state of the counter 2 changes (Fig. 2). In this case, the following switchings take place: the decoder 11 closes the memory register 12, thereby fixing the previous code combination at its input, and opens the memory register 13, the multiplexer 7 turns off the outputs of the setting device 4 of the code from the second inputs

g adder 8 and connects to the last outputs of the setting device 5 of the code, the demultiplexer 10 disconnects the output of the persistent storage device 9 from the inputs of the memory register 12 and connects it to the inputs of the memory register 13 ..

Since the code setting device 5 forms at the output the phase shift code of the second output voltage of the device, then the adder code (Fig. 2), determined by the current state of the counter 3, is formed at the output of the adder 8, taking into account the phase shift between the first and the second output voltage of the device. The code corresponding to this

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The address of the discrete sample of sinusoidal voltage is fed to memory register 13. With the arrival of the next clock pulse, the state of the counter 2 changes again. In this case, the decoder 11 fixes (Fig. 2, U ,,) in the memory register 13 a discrete sampling code of the voltage of the second phase and proceeds to the service of the next next memory register. The multiplexer 7 connects to the adder 8 the next setpoint generator, and the demultiplexer 10 connects the outputs of the permanent storage device 9 to the inputs of the next memory register. Further processes are similar to the arrival of the t-th clock pulse. Upon the arrival of the t-th clock pulse, the counter 2 is zeroed, and the counter 3 is set to the next state. In this case, the decoder 11 again opens the memory register 12, the multiplexer 7 again connects the output of the master code 4 to the second inputs of the adder 8, de multiplexer 10 connects the output of the memory to memory 9 of the device 9 to the inputs of the memory register 12. At the same time, digital-to-analog converters 15–17 continuously convert code combinations at the outputs of memory registers 12–14 into a stepwise multiphase quasi-sinusoidal voltage (Fig. 2, Ug | ,,) ,, Further processes occur as described. Thus, the complete formation of the output voltages of the device occurs.

The implementation of the device in the proposed manner allows to expand it

 functionality by introducing the possibility of changing the phase shift within the required limits by a corresponding change in the code

at the outputs of the setting devices 4-6 code, while simplifying the device, due to the use of the device for

multiphase voltage of one permanent storage device.

Claims (1)

Invention Formula A master multi-phase quasi-sinusoidal voltage generator containing a clock pulse generator, a first counter, a persistent storage device programmed according to a sinusoidal law, and digital-to-analog converters according to the number of phases of the output voltage, characterized by the fact that the second counter with a division factor equal to the number of phases of the output voltage, the decoder, adder, multiplexer, demultiplexer, code adjusters and memory registers According to the number of phases of the output voltage, the output of the clock generator is connected to the input of the second counter, the outputs of which are connected to the control inputs of a multiplexer, demultiplexer and decoder inputs, one of the outputs of the second counter is also connected to the input of the first counter, the outputs of which are connected to the first the inputs of the adder, the second inputs of which are connected to the outputs of the multiplexer, the outputs - to the inputs of a permanent storage device programmed in accordance with a sinusoidal law, passages which are connected to the data inputs of the demultiplexer outputs via demudtipleksora sootvetstvuyu1tsie memory registers are connected to the inputs of digital to analog converters, the control inputs of the registers of memory connected to the respective outputs of the decoder and the multiplexer data inputs connected to the outputs of respective setting devices code. and FIG. 2 Compiled by A. Merkulova Editor S.Pekar Tehred M.Didyk Order 4241/52 Circulation 659 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production of printing company, Uzhgorod, st. Project, 4 Proofreader S. Shekmar