SU1338005A1 - Discrete phase inverter - Google Patents

Abstract

The invention relates to radio engineering and provides simplification by reducing the size of the memory block (PSU). The discrete phase shifter (DFV) contains a master oscillator (DF) 1, a divider 2 frequencies, a shaper 3 codes of basic functions, BP 4, an adder 5, a PAP 6, a low-pass filter 7, a block 8 of multipliers, a block II of the control of a frequency divider. In BP 4 recorded coefficient. Fourier for all discrete phase shifts within one pulse-following period. GG 1, the input 9 is given a control signal in the form of codes, which are the addresses of the memory cells of the GO 4. Factor. Fourier corresponds to the required phase shift. As basic functions that are multiplied by the coefficients. Fourier transforms, for example, Walsh functions can be used. As a result of adding the results of multiplication, transformation and filtering, an output 10 generates a harmonic signal, the phase of which varies discretely within the period of the 1H period. If the phase shift exceeds the period of the 1st stage, then with the help of block 11, whose operation is clear, for one signal period dividing divider 2. As a result, the output signal of the DFV is shifted by one period of the counting pulses of divider 2. A block 11 is inserted in the phase shifter, consisting of two decipherors, two RFTH elements, two RS-triggers and two elements I. 2 Il. "(L FIG ttiiof

Description

The invention relates to radio engineering and can be used to generate a harmonic signal with varying phase.

The purpose of the invention is to simplify by reducing the size of the memory block.

Figure 1 shows an electrical block diagram of a specific

azovrack; figure 2 - block diagram given on

there may be functions on W | (e), where χ; 9 t / time signal t. On 2 formi functions fore

(8-1) - (8-4) with codes about the coefficient to be calculated 15 Fourier sinus phase phase

control of the frequency divider.

The discrete phase shifter (Fig. 1) contains a master oscillator I, a frequency divider 2, forming 3 basis function codes, a memory block 4, an adder 5, a digital-analogue converter ов1.1 преобразов converter (PAP) 6, a low-pass filter 7, block 8 multipliers, input 9 controls discrete phase shifter output 10 discrete phase shifters, block 11 controls the frequency divider, input 12 of the initial installation of the control unit frequency divider.

The frequency divider control unit 11 (Fig. 2) contains nerves 13 and BTopoii 14 decalphors, the first 15 and second 16 elements OR, the first 17 and second 18 RS triggers, the first 19 and second 20 elements I.

Discrete phase shifter works as follows.

In memory block 4, Fourier coefficients are written for all discrete phase shifts within one period of the pulse of master oscillator 1. At the start of operation of the discrete phase shifter, an input of the control unit of the frequency hub is given a pulse, KOTcipbrfi, pass through the first 15 and} The second is 16 elements OR, ycTanaBJuinaeT to the zero state, the first 17 and the second 18 K5-tripleters.

If the phase shifts n oisu.od t in

the limits of the period T of the trace of the pulse are 45 one discretes at the output of memory block 4

owing to () pa 1, block 11 does not render a task for the work of divider 2. In this case, synchronously with the operation | the generator I is fed to the input 9, which are the addresses of the memory cells of block 4, in which Fourier's samples are underused. These goats1 correspond to the required phase shift and go to the first inputs of multipliers (8-1) - (8-4) included in block 8 of multipliers (the case of using four g armonic basis functions is considered). As basic functions

given on

Different functions can be used, for example, the Walt function W | (d), where i is the number of the basis function; 9 t / Tj is the normalized current time t; TD - the period of the output signal. According to the signal from the output, the divider 2 shaper 3 codes of basis functions generates Walsh functions, the second pass) 1 multipliers

(8-1) - (8-4). At their input, codes of product of the Walsch functions by the coefficients Fourier e C are formed; that can be calculated by decomposing in a series of 5 Fourier sinusoidal functions with a given phase shift of 2 oP / g

WITH; where r

sin 2- (9 - -) W; (Gjde,

the number of phase shift increments in one period of the output sieve;

n - ko1 shchestBo entered discrete phase shift.

The results of the mind} are south with t-1 in the adder 5 and after digital-analogue compression in the digital-to-analog converter 6 and filtering in filter 7 on B1, as it goes 10, a harmonic signal is generated, the phase of which is discretely changed in the master oscillator signal one .

With a phase shift exceeding the period T of the master oscillator 1, we first consider the case when the phase shift to the right of the output signal turned out to be such that it is one shift shift less than the phase shift equal to the period T. If we denote by K the number of samples in the period T, then the shift is a shift by (K-1) discrete relative} 1o, zero initial shift. When shifting 1 right more on

0

g

The code patterns are exactly the same as for the zero shift. Therefore, if appropriate measures are not taken, the phase shift of the signal on the device output to the initial zero shift will occur. But with a phase shift of (K-1) discrete, the inputs of the decoder 1 3 are from BI, the codes of block 4 are sent by the code combination corresponding to this case (K-1) to the th phase shift y. When the driver from B1.1 of the decoder 13 comes to S-input of the first RS-trigger 17, signal 1 is received and it is not powerful / 1bit in a single state.

13

open the first input the first element and 19.

When shifting to the right one more discrete, from the outputs of the memory block 4, the code combination corresponding to the zero shift of the output signal is fed to the inputs of the factors (8-1) - (8-4). The first decoder 13 extracts information that the offset is zero and the signal 1 from its output opens the first element 19 of the third input. Divider 2 frequencies in this example, in the absence of control air (the 1st division divides the input pulses by 8. In this case, we can conditionally assume that the divider 2 frequencies successively change from state to state, to, to, etc., from where it returns to state. When divisor state 2, the frequencies from the output of the second decoder 14 signal 1 through open on the first and second inputs, first element Theent 19 enters the first control input of the divider 2 frequency, which changes the division factor from 8 to 9. Therefore, by the next counting signal at its input from state 7, it goes into the state O, as with the division factor equal to In the next counting pulse, frequency divider 2 goes to state, then to, to, etc. When state 2 divider 2 frequencies from the output of the second decoder 14, through the first element OR 15, signal 1 goes to R The input of the first RS flip-flop 17, which goes to the zero state and closes a first AND gate 19. Thus, the flow returns to 1 January used. running condition. In this case, the control signal from the first control input of the frequency divider 2 is removed. Thus, a divider of 2 frequencies by one period of the signal from the output of its higher bit increases the division factor by one, which ensures a shift of the output signal by one period T of the counting pulses of the divider 2 frequencies to the right. Thus, the transition from the (K-l) -ro shift is made not to the 0th, but to the Kth shift.

If a shift to the left occurs from the (K-l) -ro shift, i.e. is established (K-2) -th shift, then from the output of the first decoder 13 through the first element

8005

1, a 15 signal is received that translates the first RS flip-flop to the initial zero state, as a result of which the output of the first element And 19 is set to a zero level signal. With further shifts to the left, the operation of the device does not differ from the operation of the device with a discrete shift of Q within the period of the signals specifying

Oscillator 1 until the phase shift is reached, when from the output of the first decoder 13 to the S input of the second RS flip-flop 18 a signal 5 is received, through which it goes into one state, opening the second element I 20 through the second input.

When shifting to the left by one more sampling, from the outputs of memory block 4, the code combination corresponding to the (K-1) th output shift of the discrete phase shifter arrives at the Q inputs of the multipliers (8-l) - (8-4). The first decoder extracts information about 5 that there is a (K-1) -th offset, and the signal from its output opens the second element AND 20 at the third input. In this example, at state 7 of splitter 2, the frequency 1 from the output of the second decoder 14, signal 1, through the second And 20 element opened on the second and third inputs, arrives at the second control input of the frequency divider 2. Frequency divider 2 changes the division factor in this example from 7, namely, by the next counting signal at its input from state 7, it goes into the state O, as with the division factor equal to 8, 0A in the D state the On the next counting pulse, frequency divider 2 goes into a state, and so on. In state 2 of divider 2, the frequency from the output of the second decoder 14 through 5 the second element OR 16 signal 1 is fed to the R input of the second RS flip-flop 18. This from the RS flip-flop goes to the zero state and closes the second element AND 20. Thus block 11 returns to its initial state. This removes the control signal from the second input of the splitter 2 frequency.

Thus, the divider 2 frequencies by one period of the signal from the output of its higher bit reduces the division factor by one, which ensures a shift of the output signal of the discrete phase shifter by one period T of the counting pulses of the divider 2

five

frequency left. Since the code combinations of the Fourier coefficients corresponding to the (K-1) th shift arrive at this time from the outputs of block 4, the transition from the output signal with the 0th phase shift to the shifted shift by one discretion is thereby made. If, on the other hand, out of the zero shift, a shift is made to the right, i.e. the first shift is set, then the first RS flip-flop 17, which is set to one at the first shift, goes to the zero state by the signal 1 from the output of the first decoder 13, through the second element OR 16 received at its R input. The output of the second element And 20 sets the signal O, the block 11 returns to the initial state, and the control signal to the second controlled input of the frequency divider 2 is not output.

Claims (1)

Invention Formula A discrete phase shifter containing a series-connected master oscillator, a frequency divider, a basic function codes generator, a multiplier unit, an adder, a digital-to-analog converter, and a low-pass filter whose output is the output of the discrete phase shifter as well as a memory block whose input is the discrete control input a phase shifter, and the first outputs are connected to the corresponding inputs of a block of multipliers, characterized in that, in order to simplify by reducing the block size five 0 five about five memory, the control unit of the frequency divider is introduced, made in the form of the first and second decoders, the first and second RS-flip-flops, the first and second OR elements and the first and second AND elements, the first inputs of the first and second OR elements, whose outputs are connected to The R inputs, respectively, of the first and second RS flip-flops, are combined and are the input of the initial setting of the frequency divider control unit, the inputs of the first decoder are connected to the second outputs of the memory unit, and the first output is connected to the S input of the first RS flip-flop, The output of which is connected to the first input of the first element I, the output of which is connected to the first control input of the frequency divider, the inputs of the second decoder is connected to the outputs of the frequency divider, the first output is connected to the second inputs of the first and second elements OR, and the second output to the second input of the first element And with the first input of the second element And, the output of which is connected to the second control input of the frequency divider, the second output of the first decoder is connected to the third input of the first element OR, the third output of the first decoder Connected to the third input of the second element And and 5-input of the second RS-flip-flop, the output of which is connected to the second input of the second element And, the third input of which is combined with the S-input of the first RS-flip-flop, and the fourth output of the first decoder is connected to the third input of the second element OR. 3 H Compiled by E. Borisov Editor I.Kishtulinets Tehred V. Kadar Proofreader L. Besknd 4142/53 Circulation 901 Subscription INPUTS USSR State Committee for inventions and discoveries 13035, Moscow, Zh-35, Raushsk nab., 4/5 Proich; 1 (printing and printing company, Uzhgorod, Projecto st., 4 15 / 7 To blanc controlled nineteen frequency divider // 18 20 Co. Bfody - abducted frequency divider 11 FIG. 2