SU1336113A1 - Storage element - Google Patents

Abstract

The invention relates to computing technology, in particular, to a cell of CMOS transistor jsax. The purpose of the invention is to increase the reliability and simplify the circuitry of the memory element, expanding the functionality of the memory element by including the second direction of recording information. The goal is achieved by the fact that the second inverter, the second, third and fourth dynamic inverters containing the first and second MIS transistors of the first conductivity type and the first and second MOS transistors conductivity with appropriate connections. This allows designing register structures with two recording directions, shift registers and counters with parallel recording at minimum hardware costs, since it is not necessary to combine feedback feedback in three Guéré the first and, second, the recording modes. 1 з, п, фг-л, 2 Il. (L

Description

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The invention relates to computing, in particular, to memory elements for memory devices.

 The purpose of the invention is to increase the reliability of the memory element.

Figure 1 shows the functional layout of the memory element; Fig 2 is a schematic diagram of a dynamic inverter.

The memory element contains the first -1, second 2, third 3, and fourth 4 dynamic inverters, the first 5 and second 6 inverters, aN1 7 and the second 8 gate inputs, the first 9 and 10 second information inputs.

Each dynamic inverter contains the first 1 1 and the second 12 SchSch transistors. The first conductivity type, the first 13 and the second 4 MOS transistors of the second conductivity type, direct gate input 15, information input 16, inverse building input 17, output 18 of the dynamic inverter.

The memory element works as follows.

The second 2 and third 3 dynamic inverters form a trigger ring. When entering the gate inputs 7 and 8 levels O, the dynamic inverters 1 and 4 are closed, and the dynamic inverters 2 and 3 are open and the previously recorded information is stored. When level I arrives at input 7 (8), a dynamic one opens, inverter 1 (4) and dynamic inverter 2 (3) closes, respectively, a pass. recording information arriving on the first (second) information input 9 (10).

Inverters 5 and 6 at the same time provide the inversion of the input strobe signals, which is necessary for the inverse gate inputs of the first 1 and fourth 4 dynamic inverters and the direct gate inputs. second 2 and third 3 dynamic inverters.

Each dynamic inverter is closed when fed to the direct gate input 15 and the inverse gate input of 17 levels O and 1, respectively. In the memory element code 18, previously installed information is stored on a parasitic capacitor (not shown).

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When entering the direct and inverse gate inputs 15 and 17 of levels 1 and O, respectively, the MOS transistors 12 and 14 open and allow the information coming in through the information input 16 to pass through the MOS transistors 11. and 13, respectively.

Claims (2)

1. A memory element comprising a first inverter and a first dynamic inverter, wherein the input of the first inverter is connected to the direct input of the first dynamic inverter and is the first gating input of the memory element, and the information input of the first dynamic inverter is the first information input of memory different By the fact that, in order to increase the reliability of the memory element, a second inverter, a second, third and fourth dynamic inverters have been introduced into it, with the outputs of the first and. The second and third dynamic inverter information inputs are connected and are the output of the memory element, the third and fourth outputs and the second dynamic inverters information input are connected, the first inverter output is connected to the inverse input of the first and direct input of the second dynamic inverter, the first input and the inverse the input of the second dynamic inverters are connected, the direct input of the third and the inverse of the fourth dynamic inverters are connected to the output of the second inverter, whose input is in The second gating input of the memory element, the information input of the fourth dynamic inverter, is the second information input of the memory element. 2.Item according to claim 1, characterized in that the dynamic inverter contains the first and second MOS transistors of the first type of spinability and the first and second MOS trans. the second type of conductivity type, the source of the first MOSFET of the first type of conduction connected to the power rail, and its drain is connected to the source of the second VDP transistor of the first conductivity type, the drain of which is It is connected to the drain of the first MOS transistor of the second conductivity type and is the output of a dynamic inverter, the source of the first MOS transistor of the second conductivity type is connected to the drain of the second NCP transistor of the second conductivity type, the source of which is connected to the bus of zero potential of the element memory and the gate is direct strobe the input of the dynamic inverter, the gate of the first MOS transistor of the first conductivity type is an inverse gate of the dynamic inverter, the gate of the second MOS transistor of the first conductivity type, is connected to the gate of the first MOS transistor of the second conductivity type and is an information input of the dynamic inverter. 1