SU1327154A1 - Method and apparatus for displaying graphic information - Google Patents

Abstract

The invention relates to automation and computing and can be used in computer-aided design and control systems as means of displaying graphical and alphanumeric, information output from a computer or storage devices. The purpose of the invention is to increase accuracy and speed. This goal is achieved in a method of displaying graphical information based on the formation of a video signal of a step-increasing and step-like periodic voltage sweep synchronously with rectangular input signals, by generating video signals as a sequence of pulses, the number and location of pulses in which are determined by the amplitude of the corresponding direct signals. a carbon input signal, the duration of which corresponds to the duration of a sequence of pulses. 1 sp.f-ly, 3 Il. (L

Description

113271

The invention relates to automation and computing and can be used in computer-aided design and control systems, nor as means of displaying graphic and alphanumeric information issued from a computer or storage device.

The purpose of the invention is to improve the accuracy and speed of the method.

Figure 1 shows the sweep path of the sweep; FIG. 2 is a block diagram of a device for displaying graphic information; FIG. FIG. 3 shows timing diagrams of the operation of the device.

The method of displaying graphical information is based on the formation of 20 stepped-incremental and step-periodic voltage sweeps, which provide the movement of the beam along the path shown in FIG. The sweep is synchronized 25 with the input signal. The amplitude of the input signal determines the code sequence of the backlight pulses. The composition and location of pulses in a sequence can be determined by Leno, for example, by analog-digital conversion methods.

In this case, it is necessary that the code sequence be synchronized with the input signal in such a way that the video pulses arrive at the CRT modulator at time points corresponding to the points a, b, c and d indicated in Fig. 1. The duration of each code sequence of video pulses must be equal to the duration of the corresponding input square-wave signal.

The device for displaying graphical information contains the first pulse generator 1, the second pulse generator 2, the first register 3, the first digital-to-analog converter 4, the second register 5, the second digital gQ analogue converter 6, the first input 7 of the device, the second device input 8, device third input 9, cathode-ray tube 10, beam deflection unit 11 along the Y coordinate, gg beam X deflection unit 12, first pulse shaper 13, second pulse shaper IA, third pulse shaper 15 pulse542

owls, fourth shaper 16 pulses, third generator 17 pulses, first element 18 And, second element 19 And, third element 20 And, fourth element 21 And, fifth element 22 And, dough element 23 And, seventh element 24 And eighth element 25 AND, first trigger 26, second trigger 27, third trigger 28, fourth trigger 29, first element 30 OR, second element 31 OR, third element 32 OR, fourth element 33 OR, fifth element 34 I.PI, counter 35 ticks, 36 luminance pulses counter, 37 rows counter, 38 frames counter, decoder 39, switch 40, third digital-to-analog th converter 41, fourth digital-to-analog converter 42, five digital-to-analog converter 43, comparison element 44, front pulse front end 45, rear pulse front down 46, third reg 47, first adder 48, second adder 49, first delay element 50, the second delay element 51, the third delay element 52, the fourth delay element 53, the fifth delay element 54, the fourth device input 55, the fifth device input 56, the device output 57.

The device works as follows.

Using the write enable signal at the second input 8 of the device, the current value of the parallel binary code X from the first input 7 of the device to the first register 3 is written and the current value of the parallel binary Y code from the third input 9 of the device to the second register 5 is written. The parallel binary code from the first register 3 is converted by the first digital-to-analog converter 4 to an analog signal and through the first adder 48, the beam deflection unit 12 along the X coordinate, the focusing-deflecting system of the CRT 10 performs the deflected the beam is X-coordinate, and the parallel binary code from the second register 5 is converted by the second digital-to-analog converter 6 to an analog signal and through the second adder 49, the beam deflection block 11 by the Y coordinate, focusing the CRT system 10 produces the beam deflection. and the Y coordinate, with the fifth input 56

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The device receives a luminance control signal.

In this way, a luminance control signal is generated by the input signal changing synchronously with the sweep.

In order to increase the accuracy of displaying information, cyclically form the second sweep signals with a twofold increase in the sampling rate for both coordinates.

The recording signal, which appeared on the second input 8 of the device, sets the first trigger 26 to the one state through the first element 5Q. The pulses from the first pulse generator 1 are fed to the input of the first element 18 I.

The first pulse from the first element 18 And enters the counter 35 cycles, from the output of which the signals go to the decoder 39. The signal from the first output of the decoder 39 through the first element 30 OR sets the third

control trigger 28 in O, fourth trigger 29 in - and through the second element 31 OR second control trigger 27 - in.

The signal from the output of the fourth trigger 29 through the fourth shaper 16 pulses is fed to the focusing system of the CRT 10 and halves the diameter of the beam of the CRT 10. As the second control trigger 27 and the third control trigger 28 are in the O state, the output of the first element 18 And through the third delay element 52 is fed to the stroke of the switch 40 and from the first output (+) of the switch 40 through the fourth element 21 Yves counter 37 lines. The parallel binary code from the counter of 37 lines is fed to the input of the third digital-to-analog converter 41, which converts the second sweep signal according to the X coordinate (see Fig. 3, Ujtion).

The second sweep signals are then summed with the sweep reference frequency signal.

The signals with the reference sampling frequency from the first digital-to-analog converter 4 and the signals with a two-fold increase in the sampling frequency from the third digital-to-analog converter 41 are summed up on the first adder 48 and fed through the beam deflection unit 12 along the X coordinate

one

five

G

five

0

five

0

five

0

five

544

on a focusing deflection system

el1 10.

The luminance control signal is then converted into a modulating signal with a fourfold increase in the sampling rate, which changes synchronously with the first and second sweep sampling signals.

If there is a video signal at the fourth input 55 of the device, it is fed to the input of the first shaper 13 pulses and the element 44 of the comparison.

The second pulse generator 2, the seventh And element 24, the luminance counter 3.6, the fifth digital-to-analog converter 43, the comparison element 44, the second pulse generator 14, the leading edge pulse-shaping generator 45, essentially form an analog-to-digital converter with recording of binary codes from the counter 36 pulses of brightness by the signal from the imager 45 of the leading edge of the pulses into the third register 47 and operates as follows. The signal from the output of the first imager 13 pulses allows the passage of pulses from the second generator 2 through the seventh element 24 And, which arrive at the counting input of the counter 36 pulses of luminance. The increasing from zero content of the counter 36 is applied to the input of a digital-to-analog converter 43, which generates a step voltage from zero to the maximum value of the amplitude of the video signal output. When the amplitude is equal, the voltage from the output of the fifth digital-to-analog converter 43 and the amplitude of the video signal voltage, the second pulse shaper 14 generates a signal at the first input of the eighth element 25 And, which enters the trailing edge 46 of the leading edge of the pulses and the 45 front edge of the pulses With the signal. With the last one, the record of the content of the counter 36 is recorded in the third register 47. The first pulse from the third generator 17 through the eighth element 25 And shifts the contents of the third register 47 to the right in one binary bit. The signal from the output of the third register 47 through the fifth element 34 OR, the third shaper 15 pulses to the CRT modulator 10, produces a damping or illumination of the beam of the CRT 10,

51

The second impulse, from the first sJieMeirra 18, goes to the input of the third element 52. delays and 35 counts in the counter. The delay of the signal on the third element 52 is necessary for switching the switch outputs to the inputs of the counter, 37 lines or 38 frame frames. The signal from the 35 clock clock output goes to the decoder 39, from the second output of which the signal confirms through the second element 31 I-UB-I installation in About the second trigger 27 and through the third element 32 OR sets to 1 the third trigger 28, which connects the first output (+) of the switch 40 through the second element 19 AND and the fourth element 33 OR to the input of the counter 38 frames Delayed on the third delay element 52 sec The second pulse arrives at the switch AO,. Since the second control trigger 27 is in the state O, the pulse from the output of the switch 40 arrives at the (+) input of the frame counter 38 through the second element 19 And the fourth element 33 IdlTM. From the output of the 38-frame counter, the parallel binary code is fed to the input of the fourth digital-to-analog converter 42.

Further, the sum of the second sweep signals with the signals of the reference sampling frequency sweep.

The signals of the reference sampling frequency of the second digital-to-analog converter 6 and the signals with a twofold increase in the sampling frequency from the fourth digital-analog converter 42 are summed at the second adder 49 and fed through the block 11 of the beam deflection along the coordinate Y to the CRT 10.

The luminance control signal is converted into a modulating signal with a fourfold sweep sampling rate, varying synchronously with the first and second sampling signals.

In this case, in the device, the second pulse from the third generator 17 through the eighth element 25 And shifts the contents of the third register 47 to the right. To one binary bit.

The signal from the input of the third register 47 through the fifth element 34 OR, the third pulse generator I5 arrives at the CRT modulator 10, produces the extinction or beam of the CRT

546

10 depending on the content coming from the exit of the third regisr 47.

Thus, the CRT beam is deflected along the Y coordinate on one raster element to the side of the magnification of the coordinate with the corresponding illumination at this point (see Fig., Point b).

The third impulse from the first element 18 And goes to the input of the third element 52 zadder; kki and in the counter 35 cycles, from the output of which to the decoder 39. From the third output of the decoder. 39 signal through the first element 30 OR sets to the third trigger 28 and through the second element 31 OR to the second trigger 27 Pulse from the output of the third delay element 52 through the switch 40 fourth element 21 And goes to the (+) input of the counter 37 lines, From the output of the counter 37 lines parallel nny code arrives at the output of the third digital-to-analog converter 41,

Next, summarize the second sweep signals with the signals of the reference sampling frequency of the sweep.

The signals of the reference sampling frequency from the first digital-to-analog converter 4 and the signals with a twofold increase in the sampling frequency from the third digital-to-analog converter 41 on the X coordinate are summed up on the first adder 48 and fed through the X-ray deflection block 32 on the CRT 10,

The luminance control signal is converted into a modulating signal with a fourfold increase in the sampling frequency, which is synchronized with the first and second sweep sampling signals.

In this case, in the device, the third pulse from the third generator 17 through the eighth element 25 And shifts the contents of the third register 47 to the right by one bit.

The signal from the output of the third register 47 through the fifth element 34 OR, the third shaper 15 of the pulses arrives at the CRT modulator 10, produces blanking and illumination of the beam of the CRT 10, depending on the content coming in, from the output of the third register 47,

Thus, the CRT beam is deviated along the X coordinate by one raster element in the direction of increasing

Coordinates with the corresponding highlight at this point (.fig., point c).

The quarter impulse from the first element. 18 And arrives at the input of the third delay element 52 and into the 35 clock counter and to the decoder 39, from the fourth output of which the signal sets to 1 second trigger 27 and through the third element 32 OR to 1, the third trigger 28, which switch the second output ( -) of the switch 40 to () the input of the counter of 38 frames,. The fourth pulse from the output of the third delay element 52 through the switch 40, the third element 20 And arrives at the (-) input of the counter of 38 frames, from the output of which the parallel binary code enters the fourth digital to analog converter 42.

Next, summarize the second sweep signals with the signals of the reference sampling frequency sweep.

The signals of the reference sampling frequency along the Y coordinate from the second digital-to-analog converter 6 and the signals with a twofold increase in the sampling frequency along the Y coordinate from the fourth digital-analog converter 42 are summed up at the second adder 49 and fed through the beam deflection unit 11 along the Y coordinate of the CRT ten.

The transform signal is converted into a modulating signal with a fourfold increase in the sampling rate, which changes synchronously with the first and second sweep discretization signals.

 At the same time, in the device a fourth pulse c, the third generator 17 through the eighth element 25 And shifts the contents of the third register 47 to the right by one bit. The signal from the output of the third register 47 through the fifth, element 34 OR, the third driver 15 pulses to the The CRT modulator 10 quenches or illuminates the CRT 10 beam, depending on the content coming from the third register 47. Thus, the CRT beam is deviated along the Y coordinate by one raster element in the direction of decreasing the coordinate with the corresponding signal. volume in this (see Fig.1, point d). The sweep forging cycle is repeated.

548

The signal from the fourth output of the de-diffracer 39 through the second delay element 51 sets the first trigger 26 and the counter to 35 cycles, and from the fourth delay element 53 sets the counter 36 of luminance pulses, the counter 37 lines, the counter 38 frames, the first register 3 from the fourth and the second register 5, and the output 57 of the device receives a signal of the readiness of the device to receive information. The third register 47 is set to O by a signal from the pulse back driver φ 46 through the fifth delay element 54, the second trigger 27 is set to O, and the third control trigger 28 is set in the next cycle with a signal from the first decoder 39, the fourth trigger 29 is set carried by the signal from the fourth delay element 53. The signal from the output of the fourth trigger 29 through the fourth shaper 16 pulses, the focusing system of the CRT 10 doubles the diameter of the beam of the CRT 10.

Thus, the method of displaying graphic information and a device for its implementation show to double the accuracy of displaying information on the X coordinate and on the Y coordinate, to increase by 4 times the resolution of displaying graphic information while maintaining the standard video bandwidth in the recording-playback path. data storage systems, for example, video-magnetic information and computing complexes, in this case the redundancy of the transmitted information decreases, the possibility of Yeni video-magnetic systems in computer-aided design and control systems.

Claims (1)

Invention Formula 1 l. A method of displaying graphic information based on the formation of video signals of step-increasing and step-periodic voltage sweeps synchronously with rectangular input signals, which is so that, in order to improve the accuracy and speed of the method, the video signals are generated in the form of a sequence of pulses , quantity and location : 9 pulses in which is determined by the amplitude of the corresponding rectangular input signal, the duration of which corresponds to the duration of the sequence of pulses, 2 "A device for implementing a method of displaying graphic information comprising successively connected first and second pulse generators, a first register and a first digital-threshold converter, a second register and a second digital-analog converter, the information input of the first register is the first input of the device, the first control the inputs of the first and second registers are the second input of the device, the information input of the second register is the third input of the device, and the beam deflection block for ordinates Y and X, connected to the deflecting system of a CRT, the modulator of which is connected to the output of the video signal maker, is different from the fact that, in order to improve the accuracy and speed of the device, it contains three pulse makers, a third pulse generator, eight And elements, four triggers, five ISh elements, a clock counter, a luminance pulse counter, row and frame counters, a decoder, a switch, a third, fourth and fifth digital-analogue converters, a comparison element, a forward front driver Likewise, a pulse front driver, a register, two adders and five delay elements, the input of the first delay element is connected to the second input of the device, the output of the first delay element is connected to the first control input of the first trigger, the output of which is connected to the first input of the first element And, the second input of which is connected to the second output of the first pulse generator, the output of the first element And is connected to the counting input of the clock counter and to the input of the third delay element. The output of which is connected to the information the first input of the switch, the first output of which is connected to the first inputs of the second and fourth And elements, the second output of the switch is connected to the first inputs of the third and fifth elements And, the fourth and n 5410 In addition, the AND elements are connected respectively to the first and second counting inputs of the row counter, the first output of which is connected to the first input of the sixth AND element, the output of which is connected to the first input of the fourth V, of the second OR element, , the output of the fourth element OR is connected to the first counting input of the frame counter, the second counting input of which is connected to the output of the third element And, the output of the frame counter is connected to the information input of the fourth digital-analogue conversion The output of which is connected to the first information input of the second adder, the third information input of which is connected to the output of the second digital-analog converter, the output of the second adder is connected to the information input of the beam deflection unit along the Y coordinate, the information input of the beam deflection unit along the coordinate X is connected to the output of the first adder, the first information input of which is connected to the output of the first digital-analog converter, the second information input of the first adder is connected to the output the third digital-to-analog converter, the information input of which is connected to the second output of the row counter, the third count input of which is connected to the output of the fourth delay element, which is the output of the device connected to the first control input of the fourth trigger, with the third control inputs of the first and second registers, with the third counting input of the counter, frames, with the first counting input of the pulse counter r.kosti, the output of the fourth delay element is connected to the first output of the decoder connected the first input of the third OR element, with the first control input of the second trigger, the input of the second delay element, whose output is connected to the second control input of the first trigger and the reset inputs, clock counter, the output of which is connected to the information input of the decoder, the second output of which is connected to the first input the second OR element and to the second input of the third OR element, the output of which is connected to the first control unit 1113 Yush. to the input of the third trigger, the first output of which is connected to the second inputs of the second and third elements And the second output of the third trigger is connected to the second inputs of the fourth, fifth and sixth elements And, the third and fourth outputs of the decoders are connected to the first and second inputs of the first element OR, the output of which is connected to the second control inputs of the third and fourth triggers and to the second input of the second OR element, the output of which is connected to the second control input of the second trigger, the output of which is connected to the control the first output of the second pulse generator is connected to the first input of the seventh element I, the second input of which is connected to the output of the first pulse generator, whose input is the fourth input of the device connected to the first information input of the comparison element, output of the seventh element And it is connected to the second control input of the luminance pulse counter, the output of which is connected to the information input of the third register and to the information input of the fifth digital-to-analog converter Whose output is connected 5412 to the second information input of the comparison element, the output of which is connected to the input of the second pulse shaper, whose output is connected to the first input of the eighth And element, and to the inputs of the leading edge of the pulses and the back edge pulse former, whose output is connected to the input of the fifth delay element, output which is connected to the first control input of the third register, the second control input of which is connected to the output of the front edge of the pulses, the third control input of the third re The source is connected to the output of the eighth element And, the second input of which is connected to the output of the third pulse generator, the control input of which is connected to the second output of the second pulse generator, the output of the third register is connected to the first input of the fifth element OR, the second input of which is the fifth input the device, the output of the fifth element OR is connected to the input of the driver of video pulses, the focusing system of the CRT is connected to the output of the fourth pulse generator, the input of which is connected to the output of the fourth trigger . P P -Ltd Oh oh oh- O - 9 o-t us.f m w 53  gh Editor M, Pandora Compiled by A.Kumekin Tehred L.Oliynyk Order 3394/48 Circulation 433Subscription VNIIPI USSR State Committee. for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader V. But ha