SU1317649A2 - Synchronous filter - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is the reduction of transient time. The filter contains switched drives 1 and 2, r-3 pulses, counter 4, selectors 5 and 6, D / A converter 7, a controlled attenuator 8, a subtractor 9, a limiter amplifier. Drives contain a reversible counter, two D-flip-flops, an EL-EXCLUSIVE-OR, an EL, RS-trigger. 5 il. N) FIG. 7

Description

eleven

The invention relates to radio engineering and can be used to filter pulsed signals with conversion to a digital code.

The purpose of the invention is the reduction of transient time

FIG. 1 shows the structural electrical circuit of the synchronous filter of FIG. 2, a structural electrical circuit of the switched storage unit | in fig. 3 - time diagrams of shy, explaining the operation of the synchronous filter § on figs. 4 and 5 - timing diagrams, explaining the operation of switched drives at the beginning of the transition process of turning on the synchronous filter o.

The synchronous filter contains commutation drives 1 and 2, a generator of 3 pulses, a counter 4, a first 5 and a second 6 selectors, a digital-to-analog converter (D / A) 7, a controlled attenuator 8, a subtractor 9, and a suppressor Yoo

Switched drive form a reversible counter 11, combinational logic unit 12 decoder. 13, D-trigger 14, element EXCLUSIVE OR ISj element And 16, additional D-trigger 17 and RS-trigger 18 "

Synchronous filter works as follows

The input signal of the synchronous filter (Fig. “Za”) is a coherent sequence of pulses following with a period of To. The synchronous filter selects L (by the number of switched drives) values of the input pulse (in FIG. 3 L 2, respectively, the number of commutations of the drives) equals two). The input signal values at all points occur in parallel.

I

Each of KOMMYTHpyejyfbix drives 1 and 2 has two outputs. The first output is formed from (t-1) lower bits of the reversible counter 11, output C of the trigger 14 and the high-order bit, reversing counter 11, the first outputs of the first 1 drives 2 and 2 represent the digit bit of the mantissa is M and the sign of the digital equivalent of the input signal considered at the moments of iT (i is the number of periods that have passed since the synchronous filter was turned on) The remaining q bits of the reversible counter are 11 "converted at

the powers of the combinational logic unit 12 and the decoder 13 to the characteristic Nj5, form the second outputs of the switched drives 1 and 2,

The first selector 5 provides alternate connection of the first outputs of the switched drives 1 and 2 to the control inputs of the DAC 7, and the second selector 6 alternately connects the second outputs of the switched drives 1 and 2 to the control inputs of the controlled attenuator 8, the connection order is determined by the output code counter 4, and the moments of connection and disconnection are set by signals (fig. 3) from the additional output of generator 3. If there are two com- plexes, accumulate: counter 4 is represented by one binary bit.

The voltage at the output of the controlled attenuator 8 (at the Alag output of the synchronous filter) is determined by the expressions:

U,

II /, 1 g max)

Mk + Mr, come ,, oz

N

MuN ,.

Max

,

from which it follows that the voltage at the analog output is synchronous

the filter at t + iT is proportional to the product of the M and N codes at the control inputs of the DAC 7, respectively, and controlled by the attenuator

The principle of operation of the synchronous filter is based on the compensation of the input voltage Ugjj (t, + + iT) voltage (iT) applied at the subtractive input of the subtractor 9, the compensation occurs after j periods T after the synchronous filter turns on, when U (t ,, +

  obl

+ iT) reaches (fig. ZD) the corresponding values Ugj ((tj + iT), i.e. becomes equal to j. With the arrival of each input pulse at each of the two points of selection of the input voltage values to the control inputs of the DAC 7 and the controlled attenuator 8 are connected to the outputs of the corresponding switched storage device 1 or 2. Suppose that from the output of the counter 4 to the control inputs of the selectors 5 and 6 the code zero arrives, with the arrival of a clock pulse (Fig. 3) the first and second outputs of the switched drive 1, respectively, through the first 5 and second 6 villages ktora connect

to the control inputs of the D / A converter 7 and the attenuator 8 to be inserted.

The gating pulse Cy should be sufficient so that by the time t, + iT of comparing the input and output signals, the transient formation of the latter at the output of the controlled attenuator 8 is completed. If the difference, + iT) Thus, turning on the siggreen filter causes the transition process to enter it in the add mode, at which the voltage on the analog output of the synchronous filter, observed at times t, + + iT, oscillates relative to the corresponding input voltage value Ug (t) - iT) synchronous filter with discrete

 Jeb.iT) max

N, 2

- (t + iT) О, then from the output of the limiting amplifier 10 to the control inputs of switched drives 1 and 2 code 1 is received. The trailing edge of the pulse at the second input of switched storage device 1 (at the counting input where U is the reference voltage Live DAC 7 |

the maximum possible value of the digital code at the control input of the controlled attenuator 8 (constant value);

the current code value at the control input of the controllable

de-reversing counter 11) at time t, + iT (FIG. 3), a low-order unit is added to the contents of reversing counter 11. If a

N

and

ex (t, + iT) - Ue, (iT) 0, then at the output of the amplifier-limiter 10 and at the time t. +

20

lax

N. code

m

Attenuator 8 at times t. +

m

Attenuator 8 at times t. +

hch

+ iTj determined by a code of order Q of accumulators 1 and 2, the transient process of switching on a synchronous filter is characterized by an increase in the absolute values of the mantissas M1 by a unit of the least significant bit with the arrival of each input pulse and an increase in the values of the characteristics N, two

with a simultaneous decrease in the values of pic + iT from the contents of the reverse

the counter 11 of the switched accumulator 25 l 1 is subtracted by the unit of the lower order. On the trailing edge of the pulse from the additional generator output 3 pulses (Fig. 3g) at time t, + iT, the counter 4 goes from zero to either one, resulting in the arrival of the second strobe pulse in the given period (.fig, 3 g ) at the time t2 + iT - sHz selectors 5 and 6 are connected to the DAC 7 and controlled atheter.

Nyuator 8, respectively, the first and the specified process continues to the second outputs of the switched storage memory of each switching storage device 1 and bodies 2 and at the anapics output of the syn-2 up to that time period of the input of the chronical filter (subtracting the input of pulses, starting from which the reader 9) to t + iT, the tracking mode is adjusted; the corresponding signal is proportional to the product of M on the N, j outputs of the switched storage device 2; Adding one to the contents of the reversing counter 11 of the switched watch. A coercive force 2 or its subtraction, which occurs at instants C + iT along the falling edge of the pulse at its counting input (fig. 3 S), is used, depends on the code at the output of limiting amplifier 10, i.e. the sign of the difference (t2 + iT) -Ug |, | (). At time tj, + iT on the falling edge of the pulse at its input (FIG. 3), the counter 4 returns to the zero state so that in the next period the herr 18 is set to zero, and D-T retains the connection order of the trigger 14 - in a single state, the Modes of switched drives 1 and. On the first and second outputs of the commutator 2 through selectors 5 and 6 to the D / A converter 7 and the Fetch drives 1 and 2, the following codes are set in the initial equal attenuator 8. state:

the value of input voltage U ,, (t, H.iT)

To reduce the time of entry into the receiver unit, set the unit to the middle of the bit grid of the N characteristic code.

Consider the specified installation codes in more detail, in the initial state of the counter 4, reversible counters 11 switched drives 1 and 2, additional D-trigger 17 and RS-trigger

Thus, turning on the sigclock filter causes a transition process to enter it in the add mode, at which the voltage on the analog output of the synchronous filter, observed at times t, + + iT, oscillates with respect to the corresponding value of the input voltage Ug (t) - iT ) synchronous filter with discrete

Where u is the reference voltage of the DAC 7 |

 Jeb.iT) max

N, 2

 U reference voltage

 U n

lax

20

N.

Attenuator 8 at times t. +

hch

+ iTj determined by a code of order Q of accumulators 1 and 2, the transient process of switching on a synchronous filter is characterized by an increase in the absolute values of the mantissas M1 by a unit of the least significant bit with the arrival of each input pulse and an increase in the values of the characteristics N, twice after each fill of 25%.

with a simultaneous decrease in the values of

 This process continues in each switched drive 1 and 2 until the period of the input pulses, beginning with which the tracking mode is set for the corresponding tracking, is used, the force 18 is set to zero, and the D trigger 14 is in the single state , On the first and second outputs of commutative drives 1 and 2, in the initial state, the following codes are established:

the value of input voltage U ,, (t, H.iT)

This process continues into the house of the switched storage device 1 and about that period of input pulses, beginning with which the tracking mode for compliance tracking is used, is used to force 18 set to zero, and D - 14 14 - to the single state, first and The second output of commutator drives 1 and 2 in the source code will be as follows:

To reduce the time of entry into the re, the indicated process continues in each switched storage device 1 and 2 until the input pulse period, beginning with which the tracking mode is set to follow the corresponding tracking, is set to zero, and the D-trigger 14 - in the single state; On the first and second outputs of the commutative drives 1 and 2, in the initial state, the following codes are established:

The unit is set to the middle of the bit grid of the N characteristic code.

Consider the specified installation codes in more detail, in the initial state of the counter 4, reversible counters 11 switched drives 1 and 2, additional D-trigger 17 and RS-trigger 13

1st exit

o00000

 -JiLm.

The mantissa code M at the digital output of the synchronous filter and its inverse value M, directly fed to the control inputs of the DAC 7, is formed as follows. (T-1) the lower bits of the mantissa M are formed by the direct outputs of the corresponding bits of the reversible counter 11, and the most significant m-th bit is formed by the inverse output of the 1st D-flip-flop 14 Since in the initial state the inverse output of the D-flip-flop 14 (figv) and at the output of the sign (most significant) bit of the reversible counter 11. 4b) there are zeros, then at the output of the element EXCLUSIVE OR 15 (FIG. 4d), and thus the output of AND 16 (FIG. 4d) contains zeroes. Consequently, with the arrival of the 1st input pulse, an additional D-trigger 17 (Fig. 4e) does not change its (zero) state and does not generate a single signal to the V input of the write resolution from the information inputs q of the bits of the reversible counter 11, those. all bits of the latter operate in the pulse counting mode of the generator 3 (FIG. 4a).

In the switched drive 1, at time t, D-flip-flop 14 at the trailing edge of the pulse at its clock input (Fig. 4a) is set to the zero state, in which a unit appears at its inverse output (Fig. 4c), the contents of the reversible counter 11 increases by one and takes the form:

ABOUT

About 00

0001

(+)

Qi .M;

and on the outputs of the switched storage unit 1, the codes are set:

1st exit about 1 O 001

m

Thus, in the switched storage device 1 after the passage of the first

76496

of the input pulse at the first input of the EXCLUSIVE OR element is zero from the high-order output of the reversing counter 11 (Fig. 46), and at the second input there is a unit from the inverse output of the D-flip-flop 14 (Fig. 4c), as a result of this, the output of the EXCELSOR OR element 15 (FIG. 4d) and a unit is also set at the first input of the AND 16 element. Since the second input of the element AND 16 is fed to the unit from the inverse output of the RS flip-flop 18 (Fig. 4g), then the information input of the additional D-flip-flop 17 after passing the first input pulse enters the unit from the output of the And 16 element (Fig. 4e) ,

With the arrival of the 2nd input pulse at time t, + T in the switched storage 1, the contents of the reversing counter 11 are again increased by. unit:

five

25

ABOUT

0010

and on the outputs of the switched storage unit 1, the codes are set:

thirty

2nd exit

1st exit

00001

0010

N,

(+)

5m

At the same moment t, + T, the additional B-trigger 17 goes into one state (Fig. 4e) and the input V of the write resolution from the information inputs q of the bits of the reversible counter 11 receives a signal allowing the write to the specified bits order code, which must provide a unit in the middle of the bit grid of the characteristic code N. At n 5, the unit must be set to the 3rd digit of the characteristic code (with

this), which means that in q

bits of the order of the reversible counter 11 must be written code OlOg 2 ,, since og, jN | 2. For the example in question, when n 5,

the order code must have a digit q 3, and to ensure the forced setting of the required order code, the information input of the 2nd bit of the order of the reversing counter 11

connected to the inverse output of the D-trigger 14, and the remaining information inputs of the bits of the reversible counter 11 are connected to the output of the high bit of the latter. The indicated connection of information inputs q of the discharge of the reversible counter 1 1 with the output of its higher bit and the inverse output of the D-flip-flop 14 is of the same type for all switched memories 1 and 2 of the synchronous filter.

At the moment t, + T with the arrival of the second impulse, due to the appearance at the output of the additional D-flip-flop 17 of the unit (Fig. 4e), the RS-flip-flop 18 is set to one state, which does not change later, and from its inverse output on, the input element And 16 (Fig. 4g), and, consequently, from the output of the element And 16 (Fig. 4e) to the information input of the additional D-flip-flop 17 arrive zeros. As a result, with the arrival of the third pulse at t + 2T of the mantissa code M, in the up-down counter 11 of the switched storage device 1 is increased by one (0011), in pa rows order zapisshaet- with code 010, and the accumulator 1 are set codes on the outputs of dial:

2nd exit

00100

,

N,

M

At the same time t, + 2Т, an additional D-flip-flop 17 returns to the zero state (FIG. 4e), which remains unchanged in the future, disabling the zero signal on the q operation of the reversible counter 1 1 in the information recording mode. inputs, t, e, the latter can work in the future only in the pulse counting mode of the generator 3 (FIG. 4a

In the switched drive 2, the unit is forced to be installed in the middle of the discharge grid of the characteristic code in the same way, but it has some differences due to the fact that at the moments the input voltage of the synchronous filter is negative.

The initial state of the reversing counter 11 of the switched storage device 2 is determined by the code:

O (+)

About 00 0

M

with the arrival of the first input pulse at time t, the unit is subtracted from the contents of the reversible counter 11 and at the same time the D-flip-flop 14 is set to the zero state, in which its inverse output has one (Fig. 5b). The contents of the reversing counter 11 of the switched drive 2 takes the form

1111 1111

(-)

M

Qi. At the output of switched storage device 2, the following codes are set:

2nd exit 0000 1,

N.

one (-)

1st exit

11111

- M

When the code of the unit in the sign bit of the reversible counter 11 (FIG. 56), the input of the decoder 13 receives not the direct code value of the order 111, but the inverse 000, which provides for the second output of the switched storage device 2 the characteristic code 00001,

Since the initial state of the switched drives 1 and 2 is the same, with the arrival of the first pulse, the additional D-flip-flop 17 of the switched drive 2 also does not change its (zero) state (Fig. 5e),

With the arrival of the second impulse, one unit is subtracted again into the content of the reversing counter 11 of the switched storage device 2.

ment t ,, + t

one

dt

1110

M

and the D-flip-flop 14 returns to the one state (the signal at its inverse output is shown in FIG. 5, c), and the codes are set at the output of the switched storage device 2:

9 .13

1st exit

1,01110

  J

 M;

m

Since, after the passage of the first pulse, there are 1 at both inputs of the EXCLUSIVE or 15 switched storage device 2, then at its output (FIG. 5d) and also at the output of the element 16 (FIG. 5d) there are 0, resulting in at time t, , + T the second D flip-flop 17 again does not change its (zero) state (FIG. 5e) and does not generate a single signal to the V resolution of the recording from the information inputs q of bits of the reversing counter 11,

After the passage of the second pulse (time t ,, + T) due to the return, as mentioned earlier, of the first P-flip-flop 14 to the one state, JC of its inverse output to the second input of the EXCLUSIVE OR 15 element enters zero (figo 5c), as a result at its output (fig, 5, g) and

—the first input of the AND element 16 is one. Since from the inverse output of the RS flip-flop 18 to the input of the element And 16 is also fed one, then

 the output of the latter to the input of the additional D-flip-flop 17 receives a unit (FIG. 5d),

one

With the arrival of the third pulse at the time t2 + 2T, one is again subtracted from the contents of the reversing counter 11 of the switched storage device 2

910

Counter 11, a signal is received that permits writing into the indicated bits of an order code that corresponds to the characteristic code containing a unit in the middle of its bit grid. The code required for this is organized by a certain connection of information inputs q bits of the order of the reversible counter 11 with the output of its higher bit and the inverse output of the D-flip-flop 14o. When the information inputs q of the order of the third pulse have passed, code 101 will be present. Moreover, at the moment, due to the appearance at the output of the additional D-flip-flop 17 of the unit (Fig. 5e), the flip-flop 18 is set to one state, which is not

Yes, the input element And 16 (Fig. 5g), and therefore, from the output of the element I 1 6 (fig. 5d), the information input of the additional D-flip-flop 17 receives zeros

As a result, with the arrival of the fourth pulse at the moment

ts + ts

value

of the mantissa code M in the reversible counter 11 of the switched storage device 2

decreases by one (1100), the code 101 is written in bits of the order, and since the unit is in the sign bit of the reversible counter 11, the code does not enter the input of the decoder 13, but

its inverse value is 010, this provides the required value of the characteristic at the second output of the commutator 2

one (-)

1101

MG

and on the outputs of the switched accumulator 2, the codes are set:

45

2nd exit 001001

one

N, (-)

1st exit about 11 00

Jl.

m

output 001

N

one

(-Y

1st exit about 1101

m:

.-J j

m

At the same time, an additional D-flip-flop 17 goes into a single state (FIG. 5e) and to the input V of the write resolution from the information inputs q of the order is reversible

At the same moment t + 3T, the additional D-flip-flop 17 returns to the zero state (FIG. 5e), in which it further remains prohibited by the zero signal at input V to work q bits of the order of the reversible counter 1.1 of the switched drive 2 records from information inputs, i.e. these bits can work in the future only in the counting mode.

1,113

Thus, in the switched storage device 2, the unit is also set to the middle of the discharge grid of the characteristic code, only in contrast to the switched storage device 1, this happens with the arrival of not the third, but the fourth pulse.

As a result of the forced setting of the characteristics, the absolute values of the voltage observed at the analog output of the synchronous filter at times t, + 1T and increase abruptly. If at the same time it remains modulo less than the corresponding input voltage, further changes in the code on the digital and voltage on the analog outputs of the synchronous filter occur in the direction of increasing their absolute values, and in the opposite case, in the direction of decreasing them until tracking mode.

912

Claims (1)

Invention Formula Synchronous filter on the author, No. 1246343, characterized in that, in order to reduce the time transients, a series-connected EXCLUSIVE OR element, the first and second inputs of which are connected respectively to the high-end output of the reversible counter and to the D-flip-flop output, is introduced into the switched drive, and the additional D-flip-flop, the clock input of which is combined with the clock input D -triggeri and the output is connected to the enable input of the recording of the bit order of the reversible counter, and the RS trigger, the output of which is connected to another input of the element I, while the output of the higher bit reversing the counter is connected to the corresponding bits of the reversible counter, the other bits of which are connected to the output of the D-flip-flop. 1 Vn VRt I 4r / r IJrdon I % lg d I i  | L / // V7 / t d /// 4; - | | L / // V7 / t Sbf / ftg - r). I 07. J. ut;