JPH06224765A - A/d converter circuit - Google Patents

Abstract

PURPOSE:To simplify the hardware configuration of the A/D converter circuit by selecting an input/output of a comparator and a subtractor or a reference voltage by the control of a switching timing of a switch and executing coding sequentially. CONSTITUTION:When an analog signal comes to an analog input terminal 1, switches SW1, SW2 are respectively simultaneously turned on, and the analog signal is stored in capacitors C1, C2. The signal of the capacitor C2 is compared with a reference voltage being a half of the full scale at a comparator 2, and in the case of signal value > reference voltage, the comparator 2 outputs a digital output H, and in the case of signal value<reference voltage, the comparator 2 outputs a digital output L and it is a head bit of the digital signal output. A SW3 receiving the level is thrown to the position of a reference voltage generator 10, a signal from a subtractor 8 is doubled and outputted, the switch SW1 is thrown to the position of (b) in the next timing and the signal is stored in the capacitor C1. Then the signal is compared again at the comparator 2 at 1/4 of the full scale equivalently and the next digital signal is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a circuit for outputting an analog quantity to a certain numerical value or converting it into a code and outputting it. In particular, it relates to a technology for simplifying the hardware configuration in the sequential encoding method.

[0002]

2. Description of the Related Art Various types of circuits are widely known as circuits for converting analog signals into digital signals.
Here, the sequential encoding method will be described. A conventional sequential encoding circuit will be described with reference to FIG. Figure 6
FIG. 4 is a block diagram of a conventional circuit. An analog signal is input from the analog input terminal 1. The comparator 2 compares this analog signal value with the signal value output from the digital-analog conversion circuit 4 (often half the full scale of the input signal level is used as an initial value). If the input signal is larger than the output of the digital-analog conversion circuit 4, the logic circuit 3 outputs a code obtained by adding 1/2 of the digital output to the previous digital output. If the input signal is smaller than the output of the digital-analog conversion circuit 4, a code obtained by subtracting 1/2 of the digital output immediately before is output. This operation is repeated for the required number of bits.

[0003]

Sequential coding is an excellent coding method that can approximately realize maximum likelihood decoding with a limited memory amount and a limited number of calculations. However, the analog-to-digital conversion circuit as described in the conventional example has a digital-to-analog conversion circuit which has a performance equal to or higher than that of the analog-to-digital conversion circuit or a digital signal, depending on the output of the comparator. A logic circuit for supplying the data is required.

With such a complicated structure, there are problems that high speed operation is difficult, cost and power consumption are large, and reliability is low.

The present invention has been made under such circumstances, and it is an object of the present invention to provide an analog / digital conversion circuit which operates at high speed with a simple hardware configuration, has a low price, consumes less power, and is highly reliable. To aim.

[0006]

The present invention is an analog-to-digital conversion circuit. Here, a feature of the present invention is that an analog input terminal, a first switching circuit in which the analog input terminal is connected to one input, and a selection output of the first switching circuit is connected to a positive input. A subtractor whose output is connected to the other input of the first switching circuit,
A reference voltage generator that generates a reference voltage, a comparator that uses this reference voltage as a negative input and the selected output as a positive input, and is switched and controlled by the output of this comparator to select the reference voltage and common potential as inputs. A second switching circuit for providing an output to the negative input of the subtractor, the output of the comparator being connected to the digital output terminal.

It is preferable that the subtractor has a gain of 2 and the reference voltage has a potential half the full scale.

The subtractor may have a gain of 1, and the reference voltage may be set to a potential half the previous reference voltage for each output of the comparator.

It is desirable to provide a circuit in which a buffer circuit and a sampling circuit are connected in series in a passage for supplying the selection output of the first switching circuit to the subtractor.

[0010]

The input / output of the comparator and the subtractor or the switching of the reference voltage is controlled by controlling the switching timing of the switches to perform the sequential encoding.

As a result, it is possible to realize an analog / digital conversion circuit which operates at high speed with a simple hardware configuration, is low in cost, consumes less power, and is highly reliable.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of the circuit of the first embodiment of the present invention.

The present invention is an analog-digital conversion circuit. Here, the features of the present invention are that the analog input terminal 1, the first switching circuit 6 to which the analog input terminal 1 is connected to one input, and the switch SW1 of the first switching circuit 6 are provided. A subtractor 8 whose selective output is connected to the positive input and whose amplified output is connected to the other input of the first switching circuit 6, and a reference voltage generator 10 which generates half the potential of full scale as a reference voltage, A comparator 2 that uses this reference voltage as a negative input and the selected output as a positive input, and a selector output that is switched and controlled by the output of this comparator 2 and that receives the selected output as the negative input of a subtractor 8. And a second switching circuit 12 for giving the output of the comparator 2 is connected to the digital output terminal 5. The gain of this subtractor 8 is 2.

Further, a circuit in which a switch SW2 and a capacitor C2 are cascade-connected as a buffer circuit 11 and a sampling circuit is provided in a passage for supplying the selection output of the first switching circuit 6 to the subtractor 8.

Next, the operation of the first embodiment of the present invention will be described. The analog input signal is input from the switch SW1 and accumulated in the capacitor C1. This capacitor C1
The signal value stored in is stored in the capacitor C2 via the buffer circuit 11 and the switch SW2. The switch SW2 and the capacitor C2 form a sampling circuit. The signal value stored in the capacitor C2 is compared with the reference voltage of the reference voltage generator 10 which is half the full scale with the maximum input level being full scale in the comparator 2, and the signal stored in the capacitor C2 is compared. If the value is larger, the comparator 2 indicates the digital logic value "H".
Is output, and if smaller, “L” is output. This is the first bit of the digital signal output.

The signal value of the capacitor C2 is simultaneously given to the terminal 91 of the subtractor 8 and the other terminal 9 of the subtractor 8 is supplied.
2 is connected to the reference voltage generator 10 or the ground via the second switching circuit 12. This second switching circuit 12
Is switched by the output of the comparator 2, switched to the reference voltage generator 10 side if the output of the comparator 2 is "H", and switched to the ground side if the output of the comparator 2 is "L". To be

Therefore, the output of the subtractor 8 has a signal value of 2
If it is larger than the 1/2 full scale, the output of the gain times the subtracter 8 of the value obtained by subtracting the 1/2 full scale value from the signal value is obtained. If the signal value is smaller than the half full scale, an output of the gain of the subtractor 8 corresponding to the signal value is obtained. Here, the gain of the subtractor 8 is double.

The output of the subtracter 8 is fed back to the input of the buffer 2 through the b side of the switch SW1 of the first switching circuit 6. The fed back signal values are again compared by the procedure as described above. At this time, since the signal value input to the comparator 2 is doubled by the subtractor 8, it is equivalently compared with 1/4 of the full scale, and the output of the comparator 2 is next to the first bit. Equivalent to a bit. Thereafter, the same procedure is repeated until the required number of bits is reached. In the first embodiment of the present invention, one conversion cycle requires 4 bits. Comparator 2 for each bit
Since the signal values input to (1) are respectively doubled by the subtracter 8, they are equivalently compared with ½, ¼, ⅛, and ⅙ of full scale.

The above procedure will be further described with reference to FIG. FIG. 2 is a flow chart showing the operation of the first embodiment of the present invention. The analog signal α is input from the analog input terminal 1 (S1). The analog signal α and the reference voltage are compared (S2). If the analog signal α is larger than the reference voltage, “H” is output from the digital output terminal 5. At the same time, the subtractor 8 subtracts the reference voltage from the analog signal α (S3). If the analog signal α is smaller than the reference voltage, the digital output terminal 5 outputs “L”.
Is output (S4). The output of the subtracter 8 is multiplied by the gain of the input, that is, doubled (S5). The above procedure is repeated until the final bit (LSB) (S6). When the final bit is reached, a new analog signal is input from the analog input terminal 1 (S1).

Next, the operation of each section in the first embodiment of the present invention will be described with reference to FIG. FIG. 3 is a time chart showing the operation of each part in the first embodiment of the present invention. When an analog signal arrives at the analog input terminal 1, the side a of the switch SW1 is closed (ON), the analog signal is taken in, and this signal value is stored in the capacitor C1. At the same time, the switch SW2 is closed, and the analog signal is accumulated in the capacitor C2 via the buffer circuit 11.
This signal value is input to the comparator 2 and full scale 2
It is compared with a one-half reference voltage. Since this signal value is larger than the reference voltage, "H" is output as a digital output. This is the first bit of the digital signal.
In response to this, the switch SW3 of the second switching circuit 12 is closed on the side of the reference voltage generator 10. The signal value of the capacitor C2 is also input to the subtractor 8, the reference voltage is subtracted, and then the signal is multiplied by the gain, that is, doubled and output. At the next timing, the switch SW1 is closed to the side b, and the output of the subtractor 8 is stored in the capacitor C1. This signal value is input to the buffer circuit 11 and compared again by the comparator 2 according to the procedure so far. At this time, since the signal value input to the comparator 2 is doubled by the subtractor 8, it is equivalently compared with 1/4 of the full scale, and the digital signal corresponding to the bit next to the first bit is Is output. In the first embodiment of the present invention, this is repeated for 4 bits to complete one conversion cycle. Since the signal value input to the comparator 2 for each bit is doubled by the subtractor 8, it is equivalent to 1/2, 1/4, 8 of the full scale.
It is a comparison with 1 / 16th.

In the first embodiment of the present invention, the analog signal is a direct current having an amplitude of 70% of full scale, and this is digitally converted with a resolution of 4 bits. The resolution is determined by the ratio of the open / close cycle of the side a of the switch SW1, the side b of the switch SW1, and SW2. In the first embodiment of the present invention, the cycle ratio is 4. From the output waveform of the digital signal, it can be seen that the digital output "HLHH" corresponding to 70% of full scale is obtained.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram of the circuit of the second embodiment of the present invention. In the second embodiment of the present invention, the gain of the subtractor 8 is set to 1,
Each time the 1-bit analog / digital conversion operation is performed, the reference voltage is changed to ½ of the previous bit. The reference voltage generator 10 is prepared in advance with the reference voltage generation circuits 9 of ½, ¼, ⅛, and ⅙ of full scale as respective reference voltages, and these are switched. This is the configuration used.

Next, the operation of the second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a time chart showing the operation of each part of the second embodiment of the present invention. When an analog signal arrives at the analog input terminal 1, the side a of the switch SW1 is closed.
When turned on, this analog signal is taken in and this signal value is stored in the capacitor C1. At the same time switch SW2
Are closed, and the analog signal is stored in the capacitor C2 via the buffer circuit 11. This signal value is input to the comparator 2 and compared with the reference voltage of ½ of full scale. Since this signal value is larger than the reference voltage, "H" is output as a digital output. This is the first bit of the digital signal. In response to this, the switch SW3 of the second switching circuit 12 is closed. The signal value of the capacitor C2 is also input to the subtractor 8, and the reference voltage is subtracted and output. At the next timing, the switch SW1 is closed to the side b, and the output of the subtractor 8 is stored in the capacitor C1. This signal value is input to the buffer circuit 11, and the procedure up to this point is executed by the reference voltage switched to ¼ of full scale to output a digital signal corresponding to the bit next to the first bit. In the second embodiment of the present invention, this is repeated for 4 bits to complete one conversion cycle. As a result, it is possible to perform sequential encoding equivalent to that of the first embodiment of the present invention.

In the second embodiment of the present invention, the reference voltage generator 1
Each reference voltage is prepared in advance in 0 and used by switching them, but it is also possible to repeatedly pass through a multiplier having a coefficient of ½.

[0025]

As described above, according to the present invention, it is possible to realize a highly reliable analog / digital conversion circuit which operates at high speed with a simple hardware structure, has a low price, consumes less power.

Comparing the amount of hardware required to realize an N-bit analog-digital conversion circuit with the conventional example, the conventional example circuit has a comparator and an N-bit digital-analog conversion circuit (2 ^N -1 pieces). Current source and switch)
And a logic circuit are required. The present invention can be realized by a comparator, a subtractor, and a control circuit.

In order to realize a speed equivalent to that of the flash type generally used as a high-speed analog-digital conversion circuit, the hardware required for the flash type is 2 ^N -1 comparators and logic circuits. And are required. The present invention can be realized by N analog-digital conversion circuits.

Since one bit is determined in one cycle of comparison and subtraction, by repeating this operation any number of times,
An analog / digital conversion circuit with an arbitrary resolution can be realized. At this time, there is no need to change the hardware configuration.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the first embodiment of the present invention.

FIG. 3 is a time chart showing the operation of each part of the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a second embodiment circuit of the present invention.

FIG. 5 is a time chart showing the operation of each part of the second embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional example.

[Explanation of symbols]

 1 analog input terminal 2 comparator 3 logic circuit 4 digital / analog conversion circuit 5 digital output terminal 6 first switching circuit 7 control circuit 8 subtractor 9 reference voltage generation circuit 10 reference voltage generator 11 buffer circuit 12 second switching Circuit 91, 92 terminal SW1, SW2, SW3 switch C1, C2 capacitor

Claims (4)

[Claims] 1. An analog input terminal, a first switching circuit having the analog input terminal connected to one input, and a selected output of the first switching circuit is connected to a positive input, the output of which is the first input. A subtractor connected to the other input of the switching circuit, a reference voltage generator for generating a reference voltage, and a comparator having the reference voltage as a negative input and the selection output as a positive input,
A second switching circuit which is switch-controlled by the output of the comparator and which receives the reference voltage and the common potential as inputs and gives a selected output to the negative input of the subtractor, and the output of the comparator is connected to the digital output terminal. An analog-to-digital conversion circuit characterized by being performed. 2. The analog-digital conversion circuit according to claim 1, wherein the subtractor has a gain of 2, and the reference voltage has a potential half the full scale. 3. The analog circuit according to claim 1, further comprising means for setting the gain of the subtractor to 1 and setting the reference voltage to a potential half the previous reference voltage for each output of the comparator.
Digital conversion circuit. 4. The analog-digital conversion circuit according to claim 2, further comprising a circuit in which a buffer circuit and a sampling circuit are connected in series in a path for supplying the selection output of the first switching circuit to the subtractor.