SU1312564A1 - Digital discriminator - Google Patents

Abstract

The invention relates to information-measuring and computing technology and can be used in systems for recording and processing random signals, in particular, can be used for processing data received from a coordinate meter. The purpose of the invention is to expand the functionality of the digital discriminator by identifying the presence of a peak and an area of extreme values of the allocated peak. The digital discriminator contains counters 3, 4, level switch 5, (L with joint venture O5 4 /

Description

Comparison blocks 6, If result register 9, control block 8, which contains pulse edge drivers, AND, OR elements, triggers. Discriminate parameter values are set not only from the value corresponding to the first

The invention relates to information-measuring and computing technology and can be used in systems for recording and processing random signals, in particular, can be used for processing data received from a coordinate meter.

The purpose of the invention is to expand the functionality by identifying the presence of the peak and the extrinsic region of the selected peak.

FIG. 1 shows a functional diagram of a digital discriminator; in fig. 2 - functional scheme of the control unit.

The digital discriminator contains input 1 of the first parameter, input 2 of the second parameter, counters 3 and 4 of the first and second parameters, a switch of 5 levels, blocks 6 and 7 of the comparison, block 8 of control, register 9 of the result, input 10 of start, outputs 11-13. discriminator.

Each of blocks 6 and 7 of the comparison contains an adder 14, a subtractor 15, registers 16 and 17, circuits 18 and 19 of the comparison, inputs 20 of the code. The control unit 8 includes a pulse front driver 21, a trigger 22, AND elements 23-28, an OR element 29-29, additional triggers 32 and 33, a back edge pulse generator 34.

The digital discriminator works as follows.

In the ISISCODE state, the counters 3 and 4 of the digital discriminator and the registers 16 and 17, which are part of blocks 6 and 7, are reset.

Before the beginning of the processing cycle of the analyzed value, the input 10 of the digital discriminator is fed

to the derived value, but also on the magnitude of the current derived value, and simultaneously using two parameters. The device also allows identification of the presence of peaks, i.e. analyze the sign of the increment of the studied curve. 2 Il.

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a high level signal, and then the informational inputs 1 and 2 begin to receive the unitary codes of the corresponding initial parameters characterizing the object or process.

These codes are supplied to the counting inputs of counters 3 and 4, respectively.

The resulting (accumulated) values of the analyzed parameters from the outputs of counters 3 and 4 are thus fed to the code inputs of blocks 6 and 7, respectively.

Blocks 6 and 7 are identical. Therefore, we consider the operation of block 6 only.

The code value of the inputs of block 6 is applied to the second groups of inputs of the adder 14 and subtractor 15 and, simultaneously, to the second groups of inputs of the circuits 18 and 19 of the comparison.

In the adder 14, the code under study is added together with the code of the step value of the discrimination level.

In the compiler 15, the difference between the code under study and the code of the step size of the discrimination level is determined.

In the actual layout of the proposed device, summers and subtractors are made on K155IMZ elements with the representation of numbers in the reverse code, and the calculations are performed in four squares.

After the transmission of the codes of the analyzed parameters to the input 10 of the digital discriminator, a low level signal is applied, according to which the outputs of the SHSh 29 element and the shaper 34 of the control unit 8 generate unlock register 9 and record the contents of the adder 14 and the subtractor 15

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registers 16 and 17, respectively, of the control, which includes the driver of blocks 6 and 7 of the back of the pulse, trigger.

In this case, in the register 16 of the block of the record of the element And and the three elements of OR, the value of the sum of the examined one compares each block of comparison contains the sum of the code and the code of the level step size, the torus, the subtractor, two registers and two discrimination, and in register 17 - comparison circuits, the inputs of the difference between the code under investigation and the second and second parameters of the discriminator code of the discriminator level step size are connected to the counting inputs of the nation.

These values set the upper and lower / o of the second parameters, the outputs of the institute bits the levels of the nearest values of the discrimina- tions are connected respectively to the target of the analyzed quantity, the first and second groups of information. The subsequent processing cycles of the output register output operations, are output similarly to the first, but The level switch moves are now connected after the signal input to the lOfS input is given by the input groups of the device adder on the codes of the element OR 29 and the subtractor of the first and second blocks and the former 34 of the control unit 8. in comparing, comparing in each block will be formed tol- signals and outputs of the adder and the subtractor in the case of co- to achieve a unified upper or lower data inputs with values 0 corresponding to the first and second PE analyte parameter. . The hysteres, the synchronous inputs of which are combined, the code of the studied para- nen, and the outputs connected to the first meters are fed to the second groups by the input groups of the first end of the comparison circuits 18 and 19, respectively, and the second and second comparison circuits, the inputs and the lower 25 Overs of which are combined with the corresponding discrimination levels, the incoming corresponding inputs of the second groups to the first groups of inputs, the corresponding adder and the subtractor are, from registers 16 and 17, the inputs of the comparison unit code, outputs

When the specified condition of the comparison circuits is reached, the information code of the corresponding circuit is compared with the 30 inputs of the control unit, the input input in the corresponding block 6 (7) of the start of the discriminator in the control unit is formed, the permission signal is fed through the back driver to the input of the block 8 control, the pulse front is connected with the counting one in which in the control unit the form-input of the trigger and the first input sends the output signal of the analyzed E5 element I, the output of the parameter resolution from the result register 9. control unit records are connected to

Discriminate parasynchronous values of block registers are compared not only from ni, the output of the output of issuing a block of the value corresponding to the first control is connected to the current output to the output value, and from the value 40 of the Result Register, whose outputs of the current output value are informational outputs they are installed simultaneously in two discriminators, which differ in parameters. This leads to the fact that, in order to expand, if one of the output values of the functional capabilities of the discriminated parameters is faster than the achievor due to the identification of the presence of its fixed value, the peak and the region of extreme values in this the selected peak will not be output to the scheme. In the control unit, at a certain slope of the curve, neither the digital discriminator entered the values of the parameters under study, the fourth, fifth and sixth elements And corresponding to a fixed value of 50 two An additional trigger and the formation of another parameter. The trailing edge of the pulse,

moreover, the outputs of the bits of the counters performula of the invention of the first and second parameters are connected

to the code inputs respectively first

The digital discriminator, containing 55 second comparison units, an informative counter of the first parameter, the counting inputs of the control unit of the second parameter, the first and second connected to the first inputs of the second, the comparative unit, the result register, the fourth and fifth element, level switch and block And, the second inputs of which are 13

Dineny with a counting trigger input, inverse output of which is connected to the second input of the first element AND, the output of which is connected to the first input of the first IZH element, the second input of which is connected to the output of the second element OR, whose inputs are connected to the codes of the elements And from the second to the fifth , the output of the first element OR is the output of the resolution of the control unit and is connected to the input of the rear edge former of the pulse, the output of which is the output of the resolution of 25646

the control unit's records, the outputs of the third and fourth elements I are connected to the installation inputs of the first g and the second additional triggers, respectively, the installation inputs of which are connected to the output of the fifth AND element, and the direct outputs are connected to the inputs of the third 1 SHI element and the sixth, fO element I, the outputs of which are respectively the outputs of the presence of a peak and an extremum region of the discriminator's allocated peak.

VNIIGM Order 1972/47 Circulation 673

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Random polygons pr-tie, Uzhgorod, st. Project, 4

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Claims (1)

Claim A digital discriminator containing 55 a counter of the first parameter, a counter of the second parameter, the first and second comparison blocks, the result register, the level switch and the block of the first and second registers respectively, whose sync inputs are combined, and the outputs are connected to the first groups of inputs, respectively, of the first and second comparison circuits, the inputs of the second groups of which are combined with the corresponding inputs of the second groups of the adder and the subtractor and are the inputs of the code of the comparison unit, the outputs of the comparison circuits are information inputs of the control unit, the discriminator trigger input in the control unit via the trailing edge edge former is connected to the counting input of the trigger and the first input of the first element AND, the write enable output of the control unit is connected to the sync inputs of the registers of the comparison unit, the output enable output of the control unit is connected to the sync input of the result register, outputs which are information outputs of the discriminator, characterized in that, in order to expand the functionality of the discriminator through identification In contrast to the peak and the region of extreme values of the selected peak, the fourth, fifth, and sixth AND elements, two additional triggers, and a pulse tracer are introduced into the digital discriminator control unit, and the outputs of the bits of the counters of the first and second parameters are connected to the code inputs of the first and second comparison blocks, respectively , the information inputs of the control unit are connected to the first inputs of the second, third, fourth and fifth elements And, the second inputs of which are combined with the counting input of the trigger, and the versioned output of which is connected to the second input of the first AND element, the output of which is connected to the first input of the first OR element, the second input of which is connected to the output of the second OR element, whose inputs are connected to the outputs of the second and fifth AND elements, the output of the first OR element is the permission output the issuance of the control unit and is connected to the input of the driver of the trailing edge of the pulse, the output of which is the output of permission 1313564 for writing 6 control units, the outputs of the third and fourth elements And are connected to the inputs ki in one state, respectively, of the first 5 and the second additional triggers, the inputs of which are set to ”0 are connected to the output of the fifth AND element, and the direct outputs are connected to the inputs of the third · OR element and the sixth · 10 And element, the outputs of which are respectively the outputs of the peak and the extremum region of the selected discriminator peak. VNIIIPI Order 1972/47 Circulation 673 Subscription Custom polygr. ave, city of Uzhhorod, st. Project, 4