SU1310988A1 - Multimotor electric drive - Google Patents

Abstract

The invention relates to electrical engineering and can be used for frequency control of traction motors of rolling stock. The aim of the invention is to increase the efficiency of an electric motor by reducing the unevenness of the periods of the supply voltage. This goal is achieved through the use of a third frequency divider 15 with a high division factor. In addition, the introduction of a digital adder 12, the first 7 and the second 8 reversible counters and converters 9,10 code - frequency provides high accuracy of frequency control in transient conditions. 1 il. i (L with CD oo oo

Description

j13

 The invention relates to electrical engineering and can be used for frequency control of traction motors of rolling stock.

The purpose of the invention is to increase the efficiency of an electric motor by reducing the unevenness of the periods of the supply voltage.

The drawing shows a functional diagram of a multi-motor drive.

The drive contains N asynchronous traction motors I with N sensors 2 rotational speeds on the shafts, 3 frequency converter with control unit 4, adder 5 with N + 1 summing input, subtractive input and outputs of positive and negative difference, generator 6 absolute slip, first and the second reversible counters 7.8 with K-bit output each, the first, second and third converters 9, 10 and 11 code are frequencies with K-bit and clock input each, a digital adder 12 with the first and second K-bit regular inputs, a sign input and K- bit output, first, second and third dividers 13,14 and 15 frequency RS-flip-flop 16, the logic element OR 17 and the generator 18 clock pulses. The windings of the electric motors 1 are phase-wise combined and connected to the output of the frequency converter 3, connected by an input to the control unit 4. The outputs of the N 2 speed sensors are connected to the N output terminals of the adder 5, to (N + l) -My whose summing input is connected to the generator 6 abs of slip, and to the subtracting input the output of the first frequency divider 13. The output of the positive difference of the adder 5 is connected to the summing input of the first reversible counter 7, the S input of the RS flip-flop 16 and the first input of the OR 17 logic element, the output of which is connected to the -switch input of the second reversing counter 8, whose output is bitwise - connected to the second K-bit input of a digital adder 12 and K-bit input of the second converter 10 code - frequency, the output of which is connected to the subtractive input of the second reversing counter 8 via the second frequency divider 14, the output is negative

ABOUT

9882

the difference of the adder 5 is connected to the subtracted input of the first reversible counter 7, the second input of the OR 17 logic element and the R-input RS-5 of the trigger 16, the output of which is connected to the sign input of the digital adder 12, the K-bit output of which is connected with the K-bit input of the third converter 11, the code is the frequency, the output of which through the third frequency divider 15 is connected to the input of the control unit 4. The K-bit output of the first reversible counter 7 is bit-wise connected to the first K-bit input of the digital adder 12 and the K-bit input of the first converter 9 code - frequency, the output of which is connected to the input of the first frequency divider 13. The output of the generator 18 clock pulses connected to the clock inputs of the first, second and third converters 9,10 and code II - frequency.

In the device, the unevenness of the periods of the supply voltage is reduced due to the high division ratio of the third divider 15 frequency, and as a result of addition or subtraction in the codes in the digital c-summator 12 (depending on the sign of the difference at the outputs of the adder 5, the integral of the difference found in the first the reversible counter 7 and the magnitude of the difference value, located in the second reversible counter 8), at its outputs, a frequency code is obtained that ensures the accuracy of frequency control in transient conditions.

The device works as follows.

When starting rolling stock with asynchronous traction motors, which corresponds to the transient mode of operation, the frequency from the outputs of the accelerators 2 rotational frequencies proportional to the rotational speed of the rotors of asynchronous traction motors I, goes to the corresponding inputs of the adder 5, where they are summed with each other and with the signal from generator 6 absolute slip, the frequency of which is in relation to the absolute slip frequency coefficient of proportionality, equal to the ratio of the sensor 2 speed, multiplied by the number of two tor I, connected by installing the converter. On the subtracting input of the adder 5 post0

five

0

0

five

0

five

 31

frequency through the first frequency divider 13 from the first converter 9 code drops - the frequency that converts the clock frequency to a frequency proportional to the code in the first reversing counter 7. At the output of the positive difference, and in the case of deceleration from the negative difference output, a signal appears equal to the difference of the total frequency of the rotational speed sensors 2 and the absolute slip generator 6 with the frequency at the output of the first frequency divider 13. The positive difference signal is fed to the summing input +1 of the first reversible counter 7, and at a negative difference - respectively to the subtracting input -1, Since the first reversible counter 7 counts (integrates) the pulses of the difference frequency, which is caused by the lagging frequency entering the subtracting input of the adder 5 frequency due to the time constant of the digital integrator, then in the first reversible counter 7 there is an integral of the difference, which is in static mode, i.e. if not acceleration and deceleration, it is equal to the input total frequency, and in the dynamic mode it differs by the value of the dynamic error equal to the difference at the output of the adder 5.

The frequency corresponding to the frequency difference from the outputs of the adder 5, also enters the inputs of the element OR 17, the output of which goes to the summing input +1 of the second reversing counter 8. The subtracting input -1 of this reversing counter 8 receives the frequency from the output of the second frequency divider 14, whose input is connected to the output of the second converter 10, the code is the frequency, the inputs of which are bitwise connected to the outputs of the second reversing counter 8 and the clock input connected to the clock generator 18, the difference of the second reversing counter 8 when It is equal to the size of the first reversible counter 7, and the division factor of the second frequency divider 14 is equal to the division factor of the first frequency divider 13. This is necessary in order for the weights of the codes of both reversible counters to be equal and they could be summed up or calculated

thief. The difference frequency fed to the summing input of the second reversible counter 8 increases the code stored in it, and the frequency, proportional to this code, arriving at its subtracting input reduces it, i.e. in the second reversible counter 8, an integral is calculated, the value of which at a constant frequency corresponding to the difference of the adder 5 is equal to the difference at the output of the adder 5, and when the difference changes it differs about it by the value of the dynamic error, since the second

reversible counter 8 is also a digital integrator.

Both codes from reversing counters 7 and 8 are fed to the inputs of digital adder 12 depending on the state of RS flip-flop 16 defined by the difference sign, digital adder 12 adds the code of the first reversible counter 7 to the second or subtracts the code of the second from the code of the first reversible counter 7 reversible counter 8, At the outputs of the digital adder 12, a frequency code with a lower dynamic error is obtained. This code goes around the bottom to the inputs of the third

converter code 11 is a frequency, and its clock input is fed to a clock frequency from the generator output 18 pulses of pulses, which is converted to a frequency proportional to

code, and comes from the output of the third converter 11 code - frequency to the input of the third frequency divider 15. From the output of the third frequency divider 15, the signal is fed to the input of block 4

control frequency converter 3 The output frequency of the third converter 1I code - the frequency can be very large, which allows the third divider 15 frequency c to apply

a large division ratio and. reduce the non-uniformity of the control pulses of the converter feeding the asynchronous traction motors to any necessary value.

Formula inventions

Multi-motor electric drive containing N asynchronous traction

electric motors, N rotational speed sensors mounted on the shafts of the respective electric motors and

51

connected to the corresponding N summing inputs of the adder, the absolute slip generator, the output of which is connected to the (Y + 1) th summing input of the adder, the first frequency divider, the frequency converter with a control unit, characterized in that in order to increase the efficiency of the electric motor by reducing unevenness. periods of power supply voltage, the first and second reversible counters with K bit output each, the first, second and third converters code - frequency with K-bit and clock inputs each, a digital adder with the first and second K-bit are entered inputs, a sign input and a K-bit output, the second and third frequency dividers, a clock generator, an RS trigger and an OR logic element, the adder is complete with a subtracting input and outputs of positive and negative difference, the windings of N electric motors are phase-wise combined and connected are connected to the outputs of the frequency converter, the output of the positive difference of the adder is connected to the summing input of the first reversing counter, the S input of the RS flip-flop and the first input of the OR logic element, the output of which is connected to the summing input of the second

Compiled by S.Pozdnukhov Editor M.Kelemesh Tehred L.Oleinik. Proofreader A.T. sko

1900/54

Circulation 661 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk cab., d.4 / 5

. Production and printing company, Uzhgorod, Projecto st., 4

886

reversible counter, the output of the negative difference of the adder is connected to the subtractive input of the first reversible counter, the second input of the OR gate and the R input of the RS trigger, the output of which is connected to the sign input of the digital adder, the K output of the first reversible counter is connected in series

the first K-bit input of the digital adder and the K-bit input of the first converter code - frequency, the output of which through the first frequency divider is connected to the subtractive input

the adder, the K-bit output of the second reversible counter is bit-wise connected to the second K-bit input of the digital adder and the K-bit input of the second converter code frequency, the output of which is through the second frequency divider connected to the subtracting input of the second reversible counter, K- The digital output of the digital adder is bitwise connected to the K-bit input of the third converter code - frequency, the output of which is connected to the control unit of the frequency converter through the third frequency divider, the generator output clock pulses connected to the clock inputs of the first, second and third converters code - frequency.

Claims (1)

Claim A multi-motor drive containing N asynchronous traction electric motors, N speed sensors mounted on the shafts of the respective electric motors and connected to the corresponding N totalizing inputs of the adder, an absolute slip generator whose output is connected to the (S + 1) -th totalizing input of the adder, the first frequency divider , a frequency converter with a control unit, characterized in that, in order to increase the efficiency of the electric motor by reducing unevenness. periods of supply voltage, the first and second reversible counters with a K-bit output are introduced each, the first, second and third converters are code - frequency with K-bit and clock inputs each, a digital adder with the first and second K-bit inputs, a sign input and X-bit output, second and third frequency dividers, clock generator, RS-flip-flop and logic element OR, the adder is made with subtracting input and outputs of positive and negative difference, the windings of N electric motors are phase-connected and connected to the outputs of the frequency converter, the output of the positive difference of the adder is connected to the summing input of the first reversible counter, the S-input of the RS trigger and the first input of the OR logic element, the output of which is connected to the summing input of the second reversible counter, the output of the negative difference of the adder is connected to the subtracting input of the first reversing counter, the second input of the logical OR element and the R-input of the RS trigger ', the output of which is connected to the sign input of the digital adder, the K-row output of the first is reverse about the counter is connected bitwise with the 10 first K-bit input of the digital adder and with the K-bit input of the first converter, the code is the frequency, the output of which is connected through the first frequency divider to the subtracting input 15 of the adder, the K-bit output of the second reverse counter is bitwise connected to the second K -digit input of the digital adder and with the K-bit input of the second converter, code 20 is a frequency, the output of which is connected through a second frequency divider to the subtracting input of the second reversing counter, the K-bit output is digital The adder is bitwise connected to the Redundant input of the third code-to-frequency converter, the output of which through the third frequency divider is connected to the input of the frequency converter control unit, the output of the 3-clock generator is connected to the clock inputs of the first, second, and third code-frequency converters.